IRIS-HISTEQ (histogram equalization) is a synthesizable IP core that can be used to perform automatic contrast enhancement through histogram equalization in any grayscale image. IRIS- HISTEQ IP uses only the FPGA memory, provides 8-bit I/O accuracy and is tested for real FPGA implementation using IRIDA Labs specialized test bench.
- An image histogram offers a graphical representation of the tonal distribution of the gray values in a digital image. By viewing the image’s histogram, it is possible to analyze the frequency of appearance of the different gray levels contained in the image. Histogram modiﬁcation, and in particular histogram equalization, is one of the most fundamental and most useful operations in image processing since it substantially improves the contrast of an image. This method allows the areas with low contrast to gain higher contrast by spreading out the most frequent intensity values.
- No need for external memory
- High refresh rate
- Small size
- High-clock rate
- High-definition (1080p60) resolutions
- Up to 4096 total pixels and 4096 total rows
- 8-, 10- or 12-bit input and output precision
- Support for various FPGA families
- IRIS-HISTEQ is available as a synthesizable HDL soft core for ASIC and FPGA technologies and includes all the elements that guarantee a successful embodiment in proprietary designs. In addition IRIDA Labs provides:
- - Complete product documentation including detailed specifications
- - Software bit-accurate model (C++, MATLAB/Simulink model)
- - A powerful test-bench