The Multi-Channel DMA Controller supports 1 32 independent data block / packet / stream transfers. The Direct Memory Access (DMA) Controller IP Core contains 1 - 32 DMA Controller Engines (i.e. DMA Channels), supporting a 1 32 interfaces, including AMBA AXI / AHB / APB interconnects. A customized number of DMA Controller Engines and interfaces are available.
The individual internal DMA Controller Engine services each interface at its maximum throughput, whether its an AXI4 with high data burst and width capability, or Peripheral with slower speed, narrower data width requirements.
The DMA Controller IP Core can serve as a general-purpose Programmable DMA Controller supporting many system memories and peripherals, or be sized to the user required number of DMA Engines, AMBA interconnect interfaces, and user application interfaces.
- 1 - 32 Multi-Channel High Performance DMA Controller Engines:
- High-Speed Finite State Machine Control
- High Throughput to/from Memory & Peripherals via AMBA AXI / AHB on both small and large data sets
- Dual-Port, Dual-Clock FIFO, user parameterized in Depth x Width
- Optional Dual-Port, Single-Clock FIFO design
- Optional Configurability via AMBA Slave Interface
- 1 32 User Port Interfaces
- Up to 32 DMA transfers in parallel active
- Hardware or Software Initiated Transfers
- Link-List Processor for Autonomous & Chained Block Transfers
- Arbiter with variety of Arbitration Modes including Quality of Service (QoS) and low-latency
- Individual Interface Data Widths: 8 / 16 / 32 / 64 / 128 / 256 / 512 / 1024. Data re-alignment matching interfaces with different data widths
- Programmable Data Burst Capability: 1, 4, 8, 16 on AXI3/AHB/User Interfaces. Up to 256 on AXI4
- Scatter / Gather supports non-contiguous data block transfers to a contiguous segment of memory and vice versa
- Interrupt Controller Signaling DMA Transfer Done & Diagnostics
- Fully-synchronous, synthesizable Verilog RTL core, with rising-edge clocking, no gated clocks, and no internal tri-states, for easy integration into FPGA or ASIC design flows.
- Verilog RTL Source or technology-specific netlist.
- Comprehensive testbench suite with expected results.
- Synthesis scripts.
- Installation & Implementation Guide.
- Technical Reference Manual.
Block Diagram of the AXI / AHB Multi-Channel DMA Controller