The AXI Lite IPIF is a part of the Xilinx family of Advanced RISC Machine (ARM®) Advanced Microcontroller Bus Architecture (AMBA®) Advanced extensible Interface (AXI) 4.0 control interface compatible products. It provides a point-to-point bi-directional interface between a user IP core and the AXI interconnect. This version of the AXI4-Lite IP Interface (IPIF) has been optimized for slave operation on the AXI. It does not provide support for DMA and IP Master Services.
- Supports 32-bit slave configuration
- Supports read and write data transfers of 32-bit width
- Supports multiple address ranges
- If there is a simultaneous read/write on AXI, read has the higher priority over write
- Reads to the holes in the address space returns 0x00000000
- Writes to the holes in the address space after the register map are ignored and responded with an OKAY response.
- IPIF will not perform endian conversion
- Both AXI and IP Interconnect (IPIC) are little endian.