Implements a 32-bit RISC processor for demanding embedded applications that use off-chip instruction and data memories and that may need to run a real-time operating system (RTOS) or a full operating system such as Linux or Android. Part of the royalty-free BA22 family, this processor core is extremely competitive in terms of high performance and low power consumption, and has best-in-class code density (yielding very small program size).
The core has Instruction and Data Memory Management Units (MMUs) and Caches, dedicated buses for on-chip instructions and data memories, and an AMBA® AHB™ or Wishbone system bus interface. Optional floating point, divider and multiply–accumulate units benefit DSP applications. The core includes up to 32 general purpose registers (GPRs), a tick-timer (TTimer), a programmable interrupt controller (PIC), an advanced power management unit (PMU), and an optional debug unit (DBGU). Additional microcontroller peripherals may be ordered for pre-integration and delivery with the core, individually or in a complete platform. IP Integration Services are also availa-ble to help integrate any BA22 processor configuration with memory controllers, image compression, or other CAST IP cores.
The processor’s BA2 instruction set is relatively simple and extremely compact. Pro-graming is facilitated with the included C/C++ tool chain; Eclipse IDE; architectural simulator; and ported C libraries, RTOSs, and OSs.
The BA22-AP synthesizes to 35k gates in a 90nm technology, can be clocked with more than 300MHz in a 65nm technology and provides as many as 1.41 DMIPS/MHz. The core is delivered, with a complete software development environment under Eclipse IDE, and its users get access to already ported real operating systems (Linux, Android, eCOS and uClinux) and libraries.
The BA22 family of processors has been designed for easy reuse and integration, has been rigorously verified, and is production proven. Contact CAST Sales for details.
Features
- High Performance 32-bit CPU
- 1.41 DMIPS/MHz
- Single-cycle execution on most instructions
- Fast and precise internal interrupt response
- Custom user instructions
- Small Silicon Footprint & Low Power Consumption
- Industry-leading code density: Compact code minimizes instruction memory area & power; 32-bit architecture reduces power-draining memory accesses
- 35k gates and low as 0.05mW/MHz on 90nm
- Fast & Flexible Memory Access
- Harvard-style, separate Instructions and Data caches
- Tightly coupled Quick Memory for fast and deterministic access to code and/or data
- Efficient Power Management
- Further reduces power consumption by 2x to 100x using dynamic clock gating for individual units
- Software controlled clock frequency in slow and idle modes
- Interrupt wake-up in doze and sleep modes
- Advanced Debug Capability
- Conventional target-debug agent with a debug exception handler
- Non-intrusive debug/trace for both RISC and system
- Complex chained watchpoint and breakpoint conditions
- Uses industry standard Amontec JTAGKey USB to JTAG interface
- Integrated Peripherals
- Standard:32 bit tick timer, programmable interrupt controller with 32 maskable interrupt sources
- Optional Peripherals
- AMBA bus infrastructure
- Microcontroller peripherals such as GPIO. UART, Real-Time Clock, and Timers
- Serial communication cores such as I2C and SPI
- Memory controllers, interconnect IP and more
- Easy Software Development
- Eclipse IDE for Windows, Linux
- ANSI C/C++ compiler, debugger, linker, assembler, & utilities
- Architectural simulator
- Ported libraries & RTOS
Deliverables
- Verilog RTL source code
- Verilog Testbench
- Silicon-proven Reference SoC/ASIC Design
- Software development tools for Cygwin on Windows and Linux, with Eclipse IDE interface
- Operating systems and board support package
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