The JPEG-D-X core is a standalone and high-performance JPEG decoder for still image and video decompression applications. Compliance¹ with the Baseline and the Extended Sequential DCT modes of the ISO/IEC 10918-1 JPEG standard makes the JPEG-D-X core suitable for interoperable systems and devices.
In addition to decoding standard compliant Baseline and Extended JPEG streams, the core is also capable of decompressing the video payload of many (de facto) standard motion JPEG container formats.
The core is designed with easy to use, fully controllable and FIFO like, streaming input and output interfaces. Being carefully designed and rigorously verified, the JPEG-D-X is a reliable and easy to integrate core. Its deliverables include a complete verification environment and a bit-accurate software model.
- Baseline & Extended ISO/IEC 10918-1 JPEG Compliance
- Up to four Huffman Tables (two DC, two AC)
- Up to four 8-bit or 16-bit Quantization Tables
- Up to four color components
- 8-bit and 12-bit per sample
- Supports all possible scan configurations and all JPEG formats for input data
- Supports any image size up to 64K x 64K
- Supports restart markers.
- Limitations with Respect to the ISO/IEC 10918-1 JPEG Standard
- Up to 4 image components are supported.
- Supported sampling factors: 1, 2 and 4.
- Up to 4 (2 DC and 2 AC) Huffman Tables are supported.
- DNL markers are not supported.
- Additional Processing Capabilities
- Motion JPEG payload decoding
- Ease of Integration
- Registered I/O ports
- Simple, microcontroller like, programming interface
- High speed, flow controllable, streaming I/O data interfaces
- Simple and FIFO like
- Avalon-ST™ compliant (read latency 0)
- Standalone operation
- Automatic self-programming by JPEG markers parsing Marker errors catching features
- Broadcasting of decoded image parameters for controlling system peripherals, such as a block-to-raster scan converter
- Trouble-Free Technology Map and Implementation
- Fully portable HDL source code
- No internal tri-states
- Scan-ready design
- Strictly positive edge triggered design using D-type only Flip-Flops
- Fully synchronous operation
- No need for special timing constraints
- No false paths
- No multi-cycle paths
- No other special handling paths
- Fully portable VHDL or Verilog source code
- Extensive documentation
- Bit Accurate Model (BAM)
- Test Vector generation
- Self checking testbench environment
- Sample BAM scripts
- Synthesis scripts
- Simulation scripts
- Place & Route scripts for FPGAs
- Digital cameras and camcorders
- Portable multimedia devices
- Office automation equipment
- Multifunction printers
- Digital copiers
- Medical imaging systems
- Video production suites
- Video conference systems
- Display projection systems
- Surveillance systems
Block Diagram of the Baseline/Extended 12-bits JPEG Decoder