The JPEG-E-X core implements a high-performance image encoder that complies with both baseline and extended sequential DCT modes of ISO/IEC 10918-1 JPEG standard.
One of the fastest available JPEG cores, the JPEG-E-X provides a high-performance solution for a variety of image and video compression applications. In a typical 0.09µ process ASIC, the core requires just 69K gates reaching more than 450 MSamples/sec.
In addition to processing baseline (8-bits)/extended sequential (12-bits) JPEG streams, the core can compress non-standard motion JPEG streams. It can also be enhanced with an optional add-on bit-rate control block, which may benefit applications that have tight bandwidth constraints.
The core includes FIFO-like pixel and stream input/output interfaces. Other standard interfaces (e.g. AMBA) are available. The core is designed for reliability and ease of integration, and has been proven in a number of ASIC and FPGA designs. The deliverables include a software bit-accurate model that facilitates system on chip verification.
- Baseline/Extended Sequential ISO/IEC 10918-1 JPEG Compliance
- Programmable Huffman Tables (two DC, two AC) and
- Programmable quantization tables (four)
- Up to four color components (optionally extendable to 255 components)
- Supports all possible scan configurations and all JPEG formats for input/output data
- Supports any image size up to 64k x 64k
- Supports DNL and restart markers
- Additional Image Processing Capabilities
- Motion JPEG decoding
- Rate-Control (optional)
- Designed for Easy Integration
- Single clock per input sample for encoding
- Fully programmable through standard JPEG stream marker segments
- Automatic headers generation
- Automatic program-once encode-many operation
- Designed for High Quality
- Robust verification environment includes bit-accurate software model
- ASIC and FPGA proven in multiple designs
- Scan-ready design architecture
- The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:
- HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
- Sophisticated self-checking Testbench (Verilog versions use Verilog 2001)
- Simulation script, vectors, expected results, and comparison utility
- Software (C++) Bit-Accurate Model
- Synthesis script (ASICs) or place and route script (FPGAs)
- Comprehensive user documentation, including detailed specifications and a system integration guide