The JPEG-D core is a standalone and high-performance JPEG decoder for still image and video decompression applications.
One of the fastest available JPEG decoders, the JPEG-D can decode at Full HD (1080p30) or higher rates, even in FPGA devices. Full compliance with the Baseline Sequential DCT mode of the ISO/IEC 10918-1 JPEG standard makes the JPEG-D core ideal for interoperable systems and devices such as portable multimedia devices, home entertainment devices, office automation equipment, video conference systems and remote surveillance systems.
In addition to decoding standard Baseline JPEG streams, the core is also capable of decompressing the video payload of many (de facto) standard motion JPEG container formats.
The core is designed with easy to use, fully controllable and FIFO-like, streaming input and output interfaces. Being carefully designed, rigorously verified and silicon-proven, the JPEG-D is a reliable and easy to integrate core. Its deliverables include a complete verification environment and a bit-accurate software model.
Features
- Baseline ISO/IEC 10918-1 JPEG Compliance
- Up to four Huffman Tables (two DC, two AC)
- Up to four Quantization Tables
- Up to four color components
- Supports all possible scan configurations and all JPEG formats for input data
- Supports any image size up to 64K x 64K
- Supports DNL and restart markers
- Additional Processing Capabilities
- Motion JPEG payload decoding
- Ease of Integration
- Registered I/O ports
- Simple, microcontroller like, programming interface
- High speed, flow controllable, streaming I/O data interfaces
- Simple and FIFO like
- Avalon-ST™ compliant (read latency 0)
- Standalone operation
- Automatic self-programming by JPEG markers parsing
- Marker errors catching
- Broadcasting of decoded image parameters for controlling peripherals such
- as a block-to-raster scan converter
- Easy System Implementation and Verification
- Extensive documentation
- Bit Accurate Model (BAM)
- Test Vector generation
- Self checking testbench environment
- Sample BAM scripts
- Synthesis scripts
- Simulation scripts
- Place & Route scripts for FPGAs
- Trouble-Free Technology Map and Implementation
- Fully portable HDL source code
- No internal tri-states
- Scan-ready design
- Strictly positive edge triggered design using D-type only Flip-Flops
- Fully synchronous operation
- No need for special timing constraints
- No false paths
- No multi-cycle paths
- No special handling paths
Applications
- Portable multimedia devices
- Media players
- Mobile phones
- PDAs
- Home entertainment devices
- Set-top boxes
- Network media players
- Office automation equipment
- Multifunction printers
- Digital copiers
- Medical imaging systems
- Video conference systems
- Display projection systems
- Surveillance systems
Block Diagram of the Baseline JPEG Decoder Core
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