The camerIC™ -18 camera processor IP cores are a complete 18 megapixel (MP) video and still picture input unit designed for SoCs providing image capture capability in mobile phones, Portable Media Players (PMPs) and netbooks with integrated cameras. The high-performance camera pipeline features image processing, scaling and compression functions. The integrated image signal processor (ISP) supports simple CMOS sensors with no image pre-processing and sensors with integrated YCbCr processing.
The camerIC-18 IP core is Silicon Image’s fifth generation family of camera processor IP cores. Since 2002, over 20 camera designs have been delivered for use in System-on-a-Chip (SoC) application processors for digital still cameras, mobile phone and netbooks.
The camerIC-18 IP core supports resolutions ranging from 2MP up to 18MP in a single low-cost/low-power design. To effectively deliver resolutions over 12MP, the camera processor features sophisticated bad pixel detection/correction and noise reduction techniques to ensure image quality even when paired with low cost, high-resolution CMOS sensors commonly found in mobile devices. The camerIC-18 IP core also supports wide dynamic range processing and digital image stabilization, along with an extensive set of standard features.
In addition to its digital still camera capabilities, the camera pipeline has the imaging bandwidth to support HD, 3D, 4K and higher resolution video camcorder ISP functions. A 4K resolution camcorder design with the camerIC-18 ISP running at 30 frames per second will require as few as 700k gates to implement in hardware while consuming as little as 125mW of power. The camerIC hardware design is optimized to consume as little as 30 MIPS of CPU bandwidth — making the camerIC-18 one of the industry’s highest performing, lowest cost/power camera processors.
The camerIC-18 IP core supports both parallel and serial input interfaces compatible with most CMOS sensors and several CPU and memory system interfaces. The CMOS sensor sends data to the ISP via parallel interfaces supporting ITUR BT 601 and 656 compliant video data. In addition, several serial interfaces are supported including baseline compliant CCP-2 mobile imaging architecture (SMIA) and camera serial interface (CSI-2) MIPI. When communicating with a CPU or memory, 32-bit ARM AMBA AHB master, ARM AMBA AXI and BVCI are supported.
- 12-bit camera interface for (RGB Bayer input)
- MIPI & SMIA serial input interface
- Maximum input resolution up to 18 Megapixel (4928 x 3696)
- Advanced bad pixel detection and correction on the fly
- Lens shade correction (vignetting)
- Video image stabilization support
- Auto focus measurement
- Auto white balancing
- Auto exposure support by brightness measurement
- Histogram calculation
- Flash light control
- Mechanical shutter support
- Black level compensation
- Enhanced color interpolation (RGB Bayer demosaicing)
- Sharpening / blurring / noise filter
- Color correction matrix (cross talk matrix)
- Super impose, digital zoom & continuous resize support
- Wide Dynamic Range Processing (Tone mapping)
- ITU-R BT.601 & 656 compliant video interface
- HW JPEG encoder including JFIF1.02 stream generator with programmable quantization and Huffman tables
- Display-ready RGB output in self-picture path
- Rotation in 90° steps for display-ready RGB output
- Max. 300 MHz system & max. 300 MHz sensor clock
- YCbCr 4:2:2 and 4:2:0 processing
- Frame skip support for video encoding (e.g. MPEG-4)
- Format conversion between YCbCr 4:2:2, 4:2:0, 4:1:1 and 4:1:0 formats
- Planar and semi-planar storage format for YCbCr
- ARM AMBA AHB 32-bit and ARM AMB AAXI 64-bit interfaces to systemmemory supporting up to 16 beat burst length
- Power management by software-controlled clock disabling for currently not needed submodules
- Additional features are available on request
Block Diagram of the Camera Processor IP Cores