Capless LDO with Noise Quencher™ Technology (TSMC 130nm, 100mA, excellent supply rejection)

Features

• - Input voltage (VIN): 1.5V or 1.8V (2.5/3.3V can also be supported)
• - Maximum load current (Iload): 100mA
• - Output voltage (VOUT): 1.2V (adjustable)
• - Power supply rejection ratio (PSRR): Better than 55dB at 1MHz
• - Load regulation: 0.07mV/mA
• - Line regulation: Less than 1mV/V for 100mA

Benefits

• - Adds value to your microchip with embedded power management
• - Fewer components and smaller board area (NO external capacitor)
• - Improved reliability
• - Reduced inventory and reduced BOM management overhead
• - Longer battery life (save power through integration)
• - Low risk for customer product/program with a silicon proven capless LDO IP core.

Deliverables

• - Datasheet and user’s guide with integration guidelines
• - Behavioral simulation model
• - Schematics and/or spice netlist
• - Layout (GDSII)
• - Integration and test support