The Configurable AXI DDR/DDR2 SDRAM controller supports both Single Data Rate (SDR) and Double Data Rate (DDR/DDR2) SDRAM devices and all power-saving features for Mobile SDR/DDR-SDRAM devices.
Entering AXI Write & Read Commands are stacked up in separated Command Buffers (Write & Read Acceptance Capabilities) while corresponding data are stacked up into dedicated buffers. Transactions with different ID Tags are treated through separated “Virtual Ports” with automatic allocation of buffers. According to the application requirements, the generic parameters listed in Table 1 can be configured before synthesis, allowing customers to make the best possible trade-off between performance and area.
All commands are managed by a common arbiter and SDRAM Controller. The SDRAM Controller is able to optimize the bandwidth when successive or concurrent operations are required: the controller can manage up to 4 (8 for DDR2) open banks and to interlace PRECHARGE, ACTIVE & READ/WRITE commands to different rows (PRECH & ACT commands are automatically inserted during data cycles).
- Supports AMBA 3 AXI protocol (32 or 64-bit Data Width);
- Supports SDR, DDR, DDR2, Mobile SDR & DDR memory devices (8, 16, 32 or 64-bit configurations);
- Best trade-off performance/area by defining generic parameters before synthesis;
- All parameters programmable through APB Interface;
- Clocking Ratio 1:1, 1:2 or 1:4 between AXI & SDRAM Interfaces;
- Very low power consumption can be obtained by gating several internal clocks;
- Able to interface with an EBI (External Bus Interface);
- Compliant with DDR PHY Interface Specification (DFI) version 1.0;
- Simulation model