The PCI Express 3.0, 2.0, 1.1 Controller IP Core with AXI interface is a high performance, highly-configurable PCI Express® interface IP compliant to the PCI Express® rev.3.0 specification. The PCI Express 3.0, 2.0, 1.1 Controller inherits the leading architecture and reliability of previous generations of PCI Express interface IP and features an AXI user interface with built-in DMA, compliant to the AMBA AXI3 and AXI4 specifications.
Features
- PCIe Interface
- Complies with the PCI Express Base 3.0 Draft Specification, rev.3.0
- Supports Endpoint configuration
- Supports x16, x8, x4, x2, x1 at Gen3, Gen2, Gen1 speeds
- Implements one Virtual Channel
- Maximum payload size of up to 4KB
- Built-in clock domain management
- PHY Interface
- PIPE 3.0 compliant
- 32-bit/250MHz in Gen3 mode
- 16-bit mode supported
- Advanced features include
- Multi-function
- AER
- ECRC
- ATS/PRI
- MSI, MSI-X
- ASPM and legacy power management
- Lane Reversal
- Hot Plug
- Atomic operations
- User Interface
- Compliant to the AMBA AXI Specification v1.0 (AXI3) and AMBA AXI Specification v2.0 (AXI4)
- Up to 8 DMA Engines
- Up to 4GB (block) or infinite length transfers (packet)
- Up to 16 outstanding requests
- Support completion reordering
- Advanced Scatter-Gather DMA modes
- Reporting into Scatter-Gather Descriptor
- Caching of descriptors to optimize throughput
- Address Translation
- Up to 16 reconfigurable address translation tables for PCIe interface
- Up to 8 reconfigurable address translation tables per AXI4 Slave interface
- Configurable Receive and Transmit Buffer sizes
- AXI-Lite Slave interface for IP configuration
- AXI-Lite Master interface to configure up to 8KB of user defined registers in AXI domain
- Multiple combination (configurable) of AXI Master and AXI Slave interfaces
- Master Descriptor interface
- Separate clock domains for each interface
- Configurable data-path (64-bits /128-bits /256-bits)
Deliverables
- XpressRICH3-AXI IP
- Synthesizable Verilog RTL source code
- Simulation libraries for functional simulation
- Verilog RTL source code for synthesis/implementation
- PCI Express Bus Functional Model
- Software design kit
- PCI Express Linux device driver (binary or source code)
- C API
- Reference design test executable and C++/Java source code
- Reference Design
- Synthesizable Verilog RTL source code
- Simulation environment and test scripts
- ASIC synthesis scripts
- Complete Documentation
- XpressRich3-AXI IP user's manual
- PCIe BFM user's manual
- SDK user's manual
- Getting Started manual
- Technical Support and Maintenance Updates
- One-year of technical support
- One-year of IP updates
Block Diagram of the PCI Express 3.0, 2.0, 1.1 Controller IP Core with AMBA AXI User Interface
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