The D16950 is a soft core of a Universal Asynchronous Receiver/Transmitter (UART) functionally identical to the OX16C950. The D16950 allows serial transmission in two modes: UART mode and FIFO mode. In FIFO mode internal FIFOs are activated allowing 128 bytes (plus 3 bits of error data per byte in the RCVR FIFO) to be stored in both receive and transmit modes. The D16950 performs serial-to-parallel conversion on data characters received from a peripheral device or a MODEM, and parallel-to-serial conversion on data characters received from the CPU. The CPU can read the complete status of the UART at any time during the functional operation. Status information reported includes the type and condition of the transfer operations being performed by the UART, as well as any error conditions (parity, overrun, framing, or break interrupt). The D16950 includes a programmable baud rate generator that is capable of dividing the timing reference clock input by divisors of 1 to (216-1), and producing a n ?ù clock for driving the internal transmitter logic. Provisions are also included to use this n ?ù clock to drive the receiver logic. The D16950 has complete MODEM-control capability, and a processor-interrupt system. Interrupts can be programmed to the user's requirements, minimizing the computing required to handle the communications link.
In the FIFO mode, there is a selectable autoflow control feature that can significantly reduce software overload and increase system efficiency by automatically controlling serial data flow through the RTS output and the CTS input signals or by XON and XOFF characters.
The core is perfect for applications, where the UART Core and microcontroller are clocked by the same clock signal and are implemented inside the same ASIC or FPGA chip, as well as for standalone implementation, where several UARTs are required to be implemented inside a single chip, and driven by some off-chip devices.
The D16950 core includes all 16450, 16550, 16650 and 16750 features and additional functions. The D16950 has ICR registers that gives additional capabilities of configuration of UART work. Data transmission may be synchronize by external clock connected to RI ( for receiver and transmitter) or to DSR ( only for receiver) pin. NMR register allows to enable 9-bit mode transmission with or without special character. Writing and reading from/to FIFO may be controls by trigger level registers. Trigger level registers may be set any value from 1 to 127.
Two DMA modes are supported: single transfer and multi-transfer. These modes allow UART to interface to higher performance DMA units, which can interleave their transfers between CPU cycles or execute multiple byte transfers.
- Software compatible with 16450, 16550, 16750 and 16950 UARTs
- Separate configurable BAUD clock line
- Configuration capability
- Two modes of operation: UART mode and FIFO mode
- Majority Voting Logic
- In the FIFO mode transmitter and receiver are each buffered with 16 / 128 byte FIFO's to reduce the number of interrupts presented to the CPU
- Adds or deletes standard asynchronous communication bits (start, stop, and parity) to or from the serial data
- In UART mode receiver and transmitter are double buffered to eliminate the need for precise synchronization between the CPU and serial data
- Independently controlled transmit, receive, line status, and data set interrupts
- Programmable baud generator
- <i> D16950 requires 2,520 Tiles in Actel's ProASIC3 Device, with -2 speed grade for 64 MHz operation
- D16950 requires 2,520 Tiles in Actel's Fusion Device, with -2 speed grade for 64 MHz operation
- D16950 requires 2,576 Tiles in Actel's IGLOO Device, with -2 speed grade for 47 MHz operation