Configurable Watchdog Timer (WD)

Features

• Two timeout outputs
• Configurable timeout interval
• Configuration register protected with lock key
• Timeout interval with 40Mhz clock:
• min: 1.6ms
• max: 1.67s
• Supports synchronous bus interfaces such as AMBA APB version 2.0
• Full synchronous design
• Synthesis Options:
• CPU readback enable
• Selectable lock key and reset key values

Benefits

• For gate-count optimization, the core can be configured to disable the configuration register read-back path. Synthesis options are included to use the core in 8, 16 and 32-bit systems. With a separate APB wrapper, the core can be used in ARM subsystems.

Deliverables

• VHDL or Verilog RTL Source Code
• Functional Testbench
• Synthesys Script
• Data Sheet
• User Guide
• Hotline Support by means of phone, fax and e-mail

Block Diagram of the Configurable Watchdog Timer (WD)