The DDR multiPHY IP is a mixed-signal PHY IP Cores that supply the complete physical interface to JEDEC standard DDR3, DDR3L (1.35V DDR3), DDR3U (1.25V DDR3), DDR2, Mobile DDR and LPDDR2 SDRAM Memories up to 1066 Mbps data rates. The DDR multiPHY is an area and feature optimized PHY that is ideal for designers who require the ultimate flexibility in regard to the type and number of DDR interfaces they require in their SoC. Once implemented in the chip, the DDR multiPHY allows the specific DDR type supported in a system to be programmed via simple software control.
The DDR multiPHYs are compiled into a hard macro that is optimized for specific foundry nodes. Each DDR multiPHY is constructed from the following libraries of components: the application specific SSTL I/O library, a master and slave DLL library and Synopsy's unique Interface Timing Module (ITM) library. The ITM library is composed of critical controller logic close to the I/Os to facilitate the transition from double data rate to single data rate domains and eliminates timing closure issues between the RTL-based Controller logic and the hard PHY IP.
The DDR multiPHY is assembled by direct cell abutment of the library components, eliminating the need for embedded clock distribution and critical signal timing matching. A key component of the DDR multiPHY is the PHY Utility Block (PUBL) that is supplied as soft IP. The PUBL contains the circuitry to provide voltage and temperature based correction to the I/O drive impedance and ODT settings, the PHY configuration registers, testability circuitry such as the at-speed loopback controller and the DFI 2.1 interface.
- All cells connect by direct abutment resulting in a complete PHY without any routing required - allows maximum flexibility to configure and place according to user requirements (data width, chip constraints, etc.)
- Uses only 4 layers of metal for ITM & DLL, 6 or more layers for the I/O cells
- PHY Utility Bock (PUB) included as a soft IP utility that includes control features such as DQS gate training, and provides support for production testing of the DDR PHY
- Low latency
- Precision analog DLLs results in ultra low jitter
- PHY Compiler available to assemble exact customer requirements for the PHY
- When combined with a DesignWare Universal DDR digital controller core and Verification IP Synopsys provides a complete multi-protocol DDR interface IP solution supporting DDR2, DDR3/3L/3U, mDDR & LPDDR2
- Scalable architecture that supports from 0 to 1066 Mbps
- DFI 2.1 interface to controller
- Flexible, hardened macro approach: Three macro libraries are used to build the PHY, the application specific I/Os, Delay Locked Loops (DLLs) and Interface Timing Module (ITM) libraries
- Verilog behavioral model
- Synopsys lib timing model
- LEF layout abstract views & GDSII layout cells
- Spice netlists for layout versus schematic (LVS) checks
- Detailed datasheets, implementation guide, IBIS models