The Double Data Rate (DDR) SDRAM Controller Core is designed for use in applications requiring high memory throughput, high clock rates and full programmability. The core accepts commands using a simple local interface and translates them to the command sequences required by DDR SDRAM devices. The core also performs all initialization, refresh and power-down functions.
The core uses bank management modules to monitor the status of each SDRAM bank. Banks are only opened or closed when necessary, minimizing access delays. Up to 32 banks can be managed at one time.
The core queues up multiple commands in the command queue. This enables optimal bandwidth utilization for both short transfers to highly random address locations as well as longer transfers to contiguous address space. The command queue is also used to opportunistically perform look-ahead activates, precharges and auto-precharges further improving overall throughput.
The core is provided with run-time programmable inputs for all memory timing parameters and configuration settings. This ensures compatibility with all DDR SDRAM configurations. The core also ssupports of 2T timing.
Add-On Cores such as a Multi-Port Front-End and Reorder Core can be optionally delivered with the core. The core is delivered fully integrated and verified with the target DDR PHY.
- High memory throughput achieved via Look-Ahead command processing, Bank Management and Auto-Precharge support
- Multi-Port Front-End supports high efficiency command reordering and multi-port interface
- ECC, RMW, and Multi-Burst add-on modules available
- Achieves high clock rates with minimal routing constraints
- Supports all standard DDR SDRAM chips and DIMMs
- Run-time configurable timing parameters and memory settings
- A variety of read capture options are supported
- Automatic generation of initialization and refresh sequences
- Supports self-refresh and powerdown modes
- Source code available
- Customization and Integration services available
Block Diagram of the DDR SDRAM Controller Core