The Universal DDR controller family consists of three high performance products, including the Universal DDR Protocol Controller (uPCTL), the Universal DDR Memory Controller (uMCTL) and the enhanced Universal DDR Memory Controller (uMCTL2). All of which support the JEDEC DDR2, DDR3, Mobile DDR and LPDDR2 SDRAMs standards.
The Universal DDR Memory Controller delivers efficient bandwidth with minimum latency and provides the designers with transparent access and complete control of the memory subsystem. The Universal DDR Protocol Controller serves the memory control needs of applications with simple transactions that do not require an internal scheduler, and can also be deployed with custom-designed memory management units. The Universal DDR Protocol Controller SoC application bus interface supports a lowest-latency "native application interface" (NIF).
The Universal DDR Memory Controller is an advanced multi-port memory controller which accepts memory access requests from up to 32 application-side host ports. Application-side interfaces can be connected to the Universal DDR Memory Controller either through the standard AMBA AXI/AHB bus interfaces or via Synopsys custom-defined Extended Native Interface ENIF). The Universal DDR Protocol Controller is also leveraged as the protocol engine for the Universal DDR Memory Controller.
The enhanced Universal DDR Memory Controller offers features such as high-priority bypass and configurable 'look-ahead.' The high-priority bypass option allows designers to improve latency by bypassing the scheduling algorithm allowing immediate access to the DRAM. The configurable 'look-ahead' feature provides intelligent scheduling to maximize throughput by prioritizing out-of-order transactions to the DRAM, allowing designers to make trade-offs between area and performance.
All three Universal DDR controllers (uPCTL, uMCTL and uMCTL2) connect to the DDR PHY via a DFI 2.1 interface to create a complete memory interface and control solution. The controllers also include software configuration registers, which are accessed through an AMBA 2.0 APB interface.
- Data rates up to 2133 Mbps in 1:2 frequency ratio, using a 533MHz controller clock and 1066MHz memory clock
- Data rates up to 1066 Mbps in 1:1 frequency ratio, using a 533MHz controller clock and 533MHz memory clock
- Match the single ported Universal DDR Protocol Controller with your own custom memory scheduler or select a the complete multi-ported Universal DDR Memory Controller offering up to 32 host ports
- Support for JEDEC standard DDR2, DDR3, LPDDR/Mobile DDR and/or LPDDR2 SDRAMs
- Compatible with Synopsys DesignWare DDR PHYs as well as other 3rd party DFI PHYs
- DFI 2.1 compliant interface to DDR PHY
- coreAssembler tool for correct-by-construction subsystem assembly, configuration, synthesis and simulation (GUI or batch scripts); coreConsultant tool for single IP configuration, synthesis and simulation (GUI or batch scripts)
- Source Verilog RTL
- Configuration-customized, automated verification tests; unencrypted Verilog test environment
- Automated synthesis using coreAssembler/coreConsultant, including support for DFT insertion and low power synthesis
- Comprehensive databook covering features, configuration, integration, software programmers guide and coreAssembler tutorial