The DDR2/DDR SDRAM PHY IP is a complete, silicon-proven, system-level PHY interface solution for ASICs, ASSPs, System-on-Chip (SoC) and System-in-Package applications requiring high-performance DDR2/DDR SDRAM interfaces operating at up to 800 Mpbs. When combined with other DesignWare controller and verification IP, Synopsys offers a silicon proven complete solution for off-chip interfaces to DDR2/DDR SDRAMs. The pre-qualified and interoperable interface unburdens developers from memory subsystem design issues that come into play when memory data rates move beyond 400 Mbps, enabling them to focus their energy on value-added development, while significantly reducing design risk and development time.
The DesignWare DDR2/DDR SDRAM PHY is offered as hard IP and is comprised of the following components:
(a) Application specific SSTL I/O library including all required buffers, filler, power, and ground cells,
(b) Master/Slave DLL library for centering clocks in data eyes and the timing of DDR data edges for write operations, and
(c) Interface Timing Module (ITM) library composed of critical controller logic close to the I/Os for greatest system performance and ease of timing closure.
Features
- Master DLL component for SDRAM command generation and general host timing
- Master/slave DLL component for SDRAM write data generation and read data capture
- SSTL_18 and SSTL_2 operating modes selected by the voltage applied to VDDQ
- Unique ITM library facilitates timing closure with synthesized logic
- Individual library elements connect by abutment - no inter-element signal routing required
- Optional DDR signal integrity service is available to assist customers with the integration of the PHY into their SoC, package and printed circuit board environments
Benefits
- Compatible with JEDEC standard DDR2 and DDR SDRAMs
- Configurable external data bus widths between 8 and 64 bits in 8-bit increments plus ECC
- Permits operating with DDR/DDR2 SDRAMs using data widths narrower than the compiled data width
- DLL operating range of 125MHz to 533MHz permitting compatibility with various speed grades of DDR2 and DDR SDRAMs
Deliverables
- Verilog behavioral model
- Synopsys lib timing model
- LEF layout abstract views & GDSII layout cells
- Spice netlists for layout versus schematic (LVS) checks
- Detailed datasheets, implementation guide, IBIS models
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