Synopsys DesignWare® DDR2/3-Lite PHY IP solutions are mixed-signal PHY IP Cores that supply the complete physical interface to JEDEC standard DDR3, DDR3L (1.35V DDR3), DDR2 and LPDDR (Mobile DDR) SDRAM Memories up to 1066Mbps data rates. The DDR2/3-Lite PHY is an area and feature optimized DDR2/3 PHY that is ideal for designers who are currently implementing DDR2 interfaces up to 1066Mbps and want the option of migrating to DDR3 when it becomes more cost effective. As part of the optimization of this PHY, a small number of the new features for DDR3 such as write leveling are not supported as they are not required at 1066Mbps and below.
The DesignWare DDR2/3-Lite PHYs are compiled into a hard macro that is optimized for specific foundry nodes. Each DDR2/3-Lite PHY is constructed from the following libraries of components: the application specific SSTL I/O library, a master and slave DLL library and Synopsy's unique Interface Timing Module (ITM) library. The ITM library is composed of critical controller logic close to the I/Os to facilitate the transition from double data rate to single data rate domains and eliminates timing closure issues between the RTL-based Controller logic and the hard PHY IP. The DDR2/3-Lite PHY is assembled by direct cell abutment of the library components, eliminating the need for embedded clock distribution and critical signal timing matching.
The DDR2/3-Lite PHY supports an optional DFI 2.1 interface to the memory controller.
- Master DLL component for SDRAM command generation and general host timing
- Master/slave DLL component for SDRAM write data generation and read data capture
- PHY Utility Bock (PUB) included as a soft IP utility that includes control features such as DQS gate training, and provides support for production testing of the DDR PHY
- Unique ITM library facilitates timing closure with synthesized logic
- Individual library elements connect by abutment - no inter-element signal routing required
- Optional DDR signal integrity service is available to assist customers with the integration of the PHY into their SoC, package and printed circuit board environments
- Compatible with JEDEC standard DDR3, DDR3L, DDR2 and LPDDR SDRAMs and provides a DFI 2.1 interface to the memory controller
- Configurable external data bus widths between 8 and 64 bits in 8-bit increments plus ECC
- Permits operating with SDRAMs using data widths narrower than the compiled data width
- DLL operating range of 100MHz to 533MHz permitting compatibility with various speed grades of DDR2 and DDR3 SDRAMs
- Verilog behavioral model
- PVT compensation state machine RTL.
- Synopsys lib timing model
- LEF layout abstract views & GDSII layout cells
- Spice netlists for layout versus schematic (LVS) checks
- Detailed datasheets, implementation guide, IBIS models