DDR2/MDDR PHY CMD/ADDR BLOCK for DIMM usage; UMC 55nm 1.0V with 2.5V device SP/RVT LowK Logic Process

This DDR I I/O, DDR II, DDR III PHY and controllers can be used to make high performance DRAM memory interconnections for System-on-Chip (SoC) applications. All these IPs are silicon proven with an operation speed of up to 1Gbps for the DDRII IP and up to 1.5Gbps for the DDRIII PHY and controller. Furthermore, the combo PHY, such as DDR I/II PHY or DDR II/III PHY, will also be available to the end-user.