The IPX-DDR2 core is a DDR2 memory controller for Virtex-5 device running up to 266 MHz and bus width of up to 64 bits. This intoPIX core reduces the number of logic resources and improves the latency of row accesses.
The user interface is a bus up to a 256-bit width running up to 133 MHz. The maximum peak rate transfer is 64 x 2 x 266 ~= 34 Gbit/s.
The physical bus width is selectable between 8, 16, 32 and 64 bits, and the user interface also selectable between 32, 64, 128 or 256 bit.
This core also guarantees efficient DDR2 accesses to the intoPIX IPX-JP2K / IPX-JP4K core.
- Slices: Less than 1500 slices for a 32-bit wide physical data-bus; user
- data bus of 128-bit
- RAMBs: Non
- DSPs: Non
- Frequency: 266MHz (533 Mbps per data bit)