Databahn is the most widely used DDR controller solution in the world, providing the optimal interface between IC designs and the DRAM memory devices. Databahn is fully configurable for performance, power, gatecount, and multi-port data arbitration, and includes an integrated PHY. Databahn supports all commercial DRAM devices including: DD3, DDR2, combo DDR3/2, and LPDDR2/1 and LPDDR2-NVM memory.
- Configuration and performance tuning is integrated into Denali's database of over 15,000 memory models. Queue sizes and bus widths are configurable for optimal size vs. performance tradeoff.
- Advanced sequencing engine helps ensure maximum performance by minimizing lost cycles and latency. Optional, state-of-the-art elements like the Ordering Engine and Prioritization Engine with selectable algorithms give the controller unparalleled performance and flexibility.
- Advanced Databahn PHY adjusts itself so that reads are captured with extra margin, and writes can be tuned to match the board designs.
- The Databahn solution enables designers to customize a memory controller core to meet performance and interface requirements for their ASIC application. Customization is supported through an online infrastructure at Denali's eMemory.com site, allowing fast efficient configuration of various performance and interface options, and also enables simulation-based performance validation. The silicon-proven Databahn IP is library independent and covers solutions from .18-micron to .08-micron technologies, and DRAM device frequencies from 100-400MHz (200-800MHz data rate).
- Deliverables include:
- RTL and synthesis scripts,
- verification testbench,
- static timing analysis (STA) scripts,
- programmable register settings,
- and documentation.