DDR3/2 SDRAM PHY in UMC 55SP25 (2.5V thick oxide)

Features

• Low latency
• Per-bit deskew and embedded PLLs for high-speed operation and improved timing budget
• DFI 2.1 compliant interface to memory controller (1:1 or 1:2 options)
• Configurable external data bus widths between 8 and 64 bits in 8-bit increments plus ECC
• Permits operating with DDR3/2 SDRAMs using data widths narrower than the compiled data width
• Support for 1 to 4 memory ranks

Benefits

• Compatible with JEDEC standard DDR3, DDR3L and DDR2 SDRAMs and provides a DFI 2.1 interface to the memory controller
• Scalable architecture that supports the speed range from DDR2-667 up to DDR3-1600
• PHY Utility Bock (PUB) included as a soft IP utility that includes control features, such as write leveling and data eye training, and provides support for production testing of the DDR3/2 PHY
• Delivery of product as a hardened Mixed-Signal macrocell components allows precise control of timing critical delay and skew paths

Deliverables

• Verilog behavioral model
• Synopsys lib timing model
• LEF layout abstract views & GDSII layout cells
• Spice netlists for layout versus schematic (LVS) checks
• Detailed datasheets, implementation guide, IBIS models

Video Demo of the DDR3/2 SDRAM PHY in UMC 55SP25 (2.5V thick oxide)

Synopsys DesignWare DDR3-2 IP Demo at 1600 Mbps