The DDR/DDR2/DDR3-SDRAM memory controller IP Core supports both Single Data Rate (SDR) and Double Data Rate (DDR / DDR2 / DDR3) SDRAM devices.
The memory controller IP Core is an assembly of modules (controller core, user ports and physical interface). According to the user needs, a top-level can be automatically generated with all modules included.
The controller core includes a multi-port arbiter and a command sequencer. It is optimized to achieve high bandwidth by mixing accesses to the different banks of the SDRAM. It generates burst of 8 data with auto-precharge option, allowing continuous data transfer in case of long bursts.
The user port includes FIFO (for both data and addresses). Each port can have a different data bus width (larger or smaller than the SDRAM bus width). The user port provides access to individual data. It manages the generation of SDRAM burst.
The user port can be configured with many different interfaces including AXI-4 and Avalon-MM.
The physical interface manages the double data rate and the source synchronous data sampling.
- Supports SDR, DDR, DDR2 and DDR3 memory devices (discrete and dims)
- Multi-port controller
- Highly configurable
- Multi-port arbiter designed to achieve high bandwidth
- Supports a wide range of FPGA (Virtex, Kintex, Artix, Spartan, Stratix, Arria, Cyclone, …)
- User Interface
- Simple generic interface
- Each port can be individually configured
- FIFO included (configurable)
- Each port can have its own asynchronous clock
- Each port can have a different data bus width
- Can be connected to PLB/OPB bus on Xilinx device (via IPIF interface)
- AXI-4, Avalon-MM, ...
- Physical Interface
- DDR/DDR2/DDR3 PHY interface is included for many FPGA
- Number of address bits, number of chip select, data width, … are configurable
- Automatically generates the initialization sequence and periodic refresh
- Optimized for burst of 8 data
- SDRAM module serial presence supported