The increasing number of sRAM instances results a growing cost of the inevitable BIST: at chip level, the additional silicon area for the fabrication testing of the sRAMs may easily represent 5% to 10% of additional area!
Reducing the impact of these expensive tests demands innovation on the market.
Fortunately, Dolphin Integration is launching a density optimized BIST as an attractive option for their RAM generators.
The HD BIST is designed to ensure the lowest area overhead together with the shortest test time: the HD BIST is 50% smaller than alternative solutions!
Dolphin Integration thus offers 2 complete testing solutions for industrial test used in fabrication:
The HD BIST (Built-In Self Test) will test the functionality of the memory during the fabrication of the SoC. With the HD BIST, SoC integrators will benefit from faster and cheaper manufacturing tests leading to a more competitive product.
The universal BISD (Built-In Self Diagnostic) allows to also test the functionality of the memory. Additionally, the universal BISD enables the SoC integrator to identify where the errors come from (process, design…). BISD is the best solution to help diagnose yield loss and define the appropriate corrective actions.
- Reduced fabrication test costs
- Short test time
- Ease of use and flexibility
- Memory performance preserved