Tessent® TestKompress® delivers the highest quality deterministic scan test with the lowest manufacturing test cost. The solution uses a patented on-chip compression technique to create scan pattern sets that have dramatically less test data volume and reduced test time on the automatic test equipment.
- Thorough testing of digital logic with scan-based patterns.
- Fast pattern generation through high-performance ATPG algorithms and distributed processing.
- A wide variety of fault models, including stuck-at, transition, path delay, multiple-detect, and more provide a thorough test program applicable to smaller geometry technologies.
- Supports low pin count test strategies (as few as one scan channel).
- Failure files can be analyzed with Tessent Diagnosis and Tessent YieldInsight.
Video Demo of the Digital scan-based testing