TranSwitch’s TXC-48147 DisplayPort?1.1a Transmitter Intellectual Property (IP) core can be used for PC , STB, DVR, Game boxes, and other variety of digital video and audio applications operating over standard DisplayPort?cables. The TXC-48147 DisplayPort?1.1a Transmitter IP core is compliant with VESA DisplayPort?1.1a and support HDCP 1.3 standards.
The TXC-48147 IP Core supports 6/8/10/12/16 bit per component (bpc) mode and operates at 1.62Gbps or 2.70 Gbps link rate with 1, 2 or 4 lanes of main link. It’s AUX channel provides a master mode at 1Mbps. TXC-48147 supports flexible resolution, refresh rate, colorimetry and bit depth configurations.
The design of these IP cores provide superior performance exceeding standards requirements for cable length and noise immunity while providing exceptionally low power consumption and small die size. The TXC-48147 DisplayPort?Transmitters provide SI UpswingTM for configuration control over pre-emphasis filtering, signal amplitude, slop control and impedance matching parameters, greatly enhancing performance. The IP Core also support special test modes that facilitate embedded testing in SoC designs. With this IP core, customers are able to bring high definition video transmission capabilities to a myriad of devices today and well into the future without incurring internal development costs and time.
Features
- Standards Compliance:
- VESA DisplayPort 1.1a
- HDCP 1.3
- Main Link:
- Support 1, 2, or 4 lanes
- Auto negotiation for 2.7Gbps or 1.62Gbps lane rate
- Flexible differential signals swap capability
- Support 6, 8, 10, 12, 16 bit-per-component (bpc) in RGB, YCbCr444/422 colorimetry formats
- AUX channel:
- Support master mode at 1Mbps
- Half-duplex bidirectional data in Manchester II coding
- Used for link control and device management
- Transparently support EDID & DDC/CI commands
- Hot-Plug Detection:
- Supports Plug & Play with link training and monitor
- Video Processing:
- Supports 18, 24, 30, 36 & 48 bits per pixel (bpp)
- VESA Display Monitor Timing standard
- CEA-861-E Video Timing
- Up/down sampling with 60dB interpolation / decimation filters
- Flexible Color Space Converter (CSC)
- Enhanced dithering engine
- Audio Processing:
- Audio sample ranges from 32 kHz to 192 kHz
- SPDIF & I2S interface
- +1msec audio delay
- SI UpSwingTM (Signal Integrate Control)
- Amplitude control
- Slop control
- Pre-emphasis control
- Programmable terminations
- Hardware-based HDCP authentication
- HDCP encryption keys in OTP ROM
- Built-in analog & digital BIST
- I2C interface supports up to 400KHz
- Flexible resolution, refresh rate, colorimetry and bit depth configurations:
- Over 1 Lane: 8-bpc YCbCr444 (24bpp) & 1920x1080i @60Hz, 6-bpc RGB (18bpp) & 1680x1050 @60Hz
- Over 4 Lanes: 16-bpc RGB (48bpp) & 2560x2048 @60Hz, 12-bpc YCbCr422 (24bpp) & 1920x1080p @120Hz, 12-bpc RGB (36bpp) & 4096x2160 @24Hz (4K digital cinema), 10-bpc RGB (30bpp) & 2560x1600 @60Hz, 8-bpc RGB (24bpp) & 2560x2048 @60Hz
Benefits
- SI Upswing(TM) for long and cheap cable support
- Flexible resolution, refresh rate, colorimetry and bit depth configurations
- hardware HDCP
- Smallest die size
- Low pwer
- Analog BIST
- High yield
- Low BOM cost
Deliverables
- Design Models
- Hard Macro
- HDL Simulation Models
- Timing Models (.lib)
- GDSII
- Physical Abstract Model (LEF)
- Soft Macro
- Netlist
- Synthesis & Timing Scripts
- System Verilog Test Bench
- Design Integration Documents
- IP Core Data Sheet
- Integration Guidelines
- Digital Place and Route Guidelines
- Core Integration Guidelines
- Simulation Environment & Timing Views
- Test Documents
- Analog Test Plan
- PHY Test Suite
- Conformance/Verification Testing
- System Level Documents
- Board Layout Reference Design
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