The DO-254 SPI Slave IP Core is primarily used to allow a microcontroller unit (MCU) to communicate with peripheral devices.
The SPI system is flexible enough to interface directly with numerous standard product peripherals from several manufacturers.
Clock control logic allows a selection of clock polarity and a choice of two fundamentally different clocking protocols to accommodate most available synchronous serial peripheral devices.
- Design Assurance Level A according to RTCA DO-254/ED-80 (April, 2000)
- Compliant to SPI Standard (Motorola's M68HC11 Reference Manual)
- Automatically detects and adjusts to the bus data rate
- Configurable phase, polarity and word size
- Simple interface to user's logic
- TMR coded for SEU immunity (optional)
- Technology independent (can be synthesized to any FPGA/CPLD vendor)
- For a fact sheet of this IP Core please go to:
- For Implementation Size and Speed please go to:
- For a VHDL example please go to:
Block Diagram of the DO-254 SPI Slave IP Core