The AXI_PCIEX1 module is a PCI Express® to AXI Bridge. It allows a system with an embedded AXI bus to be connected to an external PCI Express® Bus. The hardware item only covers digital layers of the PCI Express® bus architecture. In a typical system the main external processor is able to address the internal AXI bus used to interconnect all internal components all together. With its unique internal architecture the digital core is optimized for low gate count and low latency applications. The AXI_PCIEX1 is able to recover from SEU and to report any detected errors with the help of its embedded reliability features. Detected errors are then reported to external processor and to internal sub-system. The AXI_PCIEX1 matches major needs of any critical application and mainly those which require a DO-254 DAL-A compliance in the aerospace area.
The development has been done according to the RTCA/DO-254 ED-80 guidelines.
This component has been developed, verified and licensed by SILKAN.
- Developed according to RTCA/DO-254 ED-80 guidance. Compliant DAL A.
- Compliant with PCIe Specification 2.0 – Gen1.
- Compliant with AMBA AXI Protocol version 2.0.
- Compliant with PIPE version 1.0. PHY Interface for the PCI Express® Architecture.
- Mitigation technique:s Recover from SEU (self-healing feature) and report any detected error.
- PCI Express® Endpoint Gen 1 at 2.5 Gbps.
- One Lane (x1).
- PIPE: 16 bits interface (Optional 8 bits). PIPE Clock frequency is 250MHz in 8 bits or 125MHz in 16 bits.
- AMBA AXI4: 32 bits data/address Slave and Master Interfaces (Optional APB interface for Configuration Registers).
- Supports 6 BAR (Base Address Registers).
- Supports PCIe Power Management capability: ASPM L0s and L1.
- Optional MSI capabilities.
- Full AER capability implemented.
- Full report done to Root Complex and to user application. (ECC on data buffers, FSM monitoring)
- Implements Advanced Reliability features for critical applications.
- Optional CDC between PCIe’s clock domain and AXI’s clock domain.
- Optimized for low gate count (4-5k LE on FPGA) and low core latency.
- Configurable buffer size from 512B to 2kB depending on performance requirement.
- Technology independent Verilog RTL sources code compliant with SILKAN’s design standard.
- SystemVerilog Functional verification test-benches using best-in class BFM from Mentor Graphics with full code and functional coverage.
- Reference Design as integration example (Dry Run) on Xilinx device.
- SILKAN’s support includes technical integration, DO-254 integration and certification phases.
- IP Datasheet and Customer Requirement Specification (CRS) document.