The Dolby® Digital Decoder (CWda61) is an IP core designed to work as an engine for decoding audio streams. This IP core is supported on ASICs or FPGAs.
The IP core is implemented using the Coreworks proprietary FireWorks™ 32-bit RISC processor and the SideWorks™ reconfigurable accelerator.
The IP core commands, settings and state can be written/read by means of a configuration, control, and status register file, accessed by an AMBA APB interface. An external I2C, SPI, etc, core can be provided to drive this interface.
The IP core requires program and data memories which can be external or embedded in the chip. External cores can be provided to drive the Audio Data I/O interface to support audio formats such as SPDIF, I2S or TDM.
The codec configuration is provided via the Software Interface Protocol (SIP). The SIP is a composite structure with all the parameters required to encode or decode audio frames. The core may run continuously or frame by frame.
Features
- Compliant with the Dolby Digital Decoder Development Kit version 3.0
- Supports all specified channel modes: 1+1, 1/0, 2/0, 3/0, 2/1, 3/1, 2/2, 3/2
- Supports all specified sample rates: Fs = 32, 44.1 and 48 kHz
- Maximum 24-bit output audio resolution
- Supports all specified bit rates: 56, 64, 80, 96, 112, 128, 160, 192, 224, 256, 320, 384, 448, 512, 576, 640 kbps
- Support of karaoke aware and karaoke capable features
- Pro decoder latency: 1536/Fs (1 frame)
- Consumer decoder latency: from 288/Fs to 896/Fs
- Requires 128 kB of external memory
- Supports AMBA-AHB master interface to memory controller, APB slave interface for Configuration, Control, Status and Programming interfaces
- Easy to use multi-channel parallel TDM interfaces
- Parallel audio interfaces easy to connect to industry standard interfaces such as AES3, SMPTE337M, SPDIF, I2S/TDM or custom interfaces
- Supports burst or continuous data flows
- Parallel boot interface easy to connect to industry standard interfaces such as SPI, I2C, etc.
- Real time operation @80 MHz
Benefits
- Compact hardware implementation – fits economically in FPGAs
- Low operation frequency
- Extreme low power consumption
- Small external memory footprint
Deliverables
- Datasheet
- FPGA netlist
- Program binaries
- Implementation constraints
- Evaluation board (optional)
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