This macro from Cadence Design Systems contains dual 11- bit 440 MHz analog-to-digital converters (ADC).
Each ADC uses a successive approximation register (SAR) architecture.
The dual 11-bit ADC is powered from a 2.5V analog, a 1.2V analog, and a 1.2V digital supply. The ADC is designed to receive a differential Current Mode Logic (CML) clock and outputs 11 bits in a two’s complement format. The ADC also supplies an output clock which can be used to clock the data into registers in the core logic circuitry.
The dual ADC includes a bandgap reference and all required biasing amplifiers. This bias generation circuitry can be programmed from its nominal set point by a digital control bus. All internal reference voltages and bias currents are derived from an internal bandgap voltage.
In power down mode all circuits are turned off and the power supply current is reduced to leakage levels.
- Dual 11-bit Analog to Digital Converters
- Successive approximation register architecture
- 440 MHz nominal sample rate
- Power down mode
- Analog test bus for pre-production testing
- Optimized for the TSMC 65nm LP 8M5X2Z 1.2V/2.5V deep n-well
- Suitable for the following applications:
- Wireless Applications
- High Speed Analog to Digital Conversions
- SoC systems
- Standard Integration Views
- Integration Support