The Dual 12b 20 to 200MS/s 1.2V ADC achieves 11 ENOB conversion linearity. It is built around a fully differential proprietary enhanced pipeline converter and a digital error correction circuitry. A low noise input buffer is provided for an easier interface to your analog/RF front-end.
This Dual 12b 20 to 200MS/s 1.2V ADC IP includes an internal reference voltage generator with internal decoupling and an internal bias circuitry. The input buffer signal bandwidth (SBW) and the data converter achievable conversion speed are digitally scalable for optimal power consumption. For a better match to your specific needs, other power reduction modes are available upon request.
- UMC 90nm general purpose 1.2V CMOS process
- Single 1.2V supply
- 20 to 200 Mspls/s scalable sampling rate
- 0.5 Vp_diff input dynamic range
- Up to 100MHz input buffer signal bandwidth
- DNL = ±0.5 LSB typ., INL = ±1 LSB typ.
- SNR = 68dBFS @ Fin = 10MHz and 200MS/s
- SFDR > 72dBc @ Fin = 10MHz and 200MS/s
- Fully internal reference voltage generator and bias circuitry. No external decoupling needed.
- Proprietary architecture enhancements allowing very high conversion efficiency
- less than 1.3 mm2 core area including two input buffers, the reference generator, biasing and internal decoupling
- Power down mode
Block Diagram of the Dual 12-Bit 20 to 200MS/s 1.2V ADC, CMOS 90nm