The ConnX D2 DSP engine is a click-box option for Tensilica's benchmark-breaking Xtensa LX processor technology. The ConnX D2 option adds dual 16-bit multiply-accumulate (MAC) units and a 40-bit register file to the base RISC architecture of the Xtensa LX processor. The ConnX D2 engine utilizes two-way SIMD (single instruction, multiple data) instructions to provide high performance on vectorizable C code. It also delivers dual-MAC performance using 64-bit VLIW (very long instruction word) instructions for code that cannot be vectorized.
The ConnX D2 DSP engine delivers outstanding 16-bit fixed point "out of the box" performance on compiled C code, without the need for assembly code optimization. This allows SOC development teams to have greater flexibility in resource allocation as well as the ability to quickly change algorithms. C code optimized with TI C6x or ITU C intrinsic functions compiles directly to the ConnX D2 instruction set, allowing developers to benefit from pre-existing TI and ITU code bases.
The ConnX D2 engine is supported by the comprehensive Eclipse-based Xtensa Xplorer software development environment containing everything from a source code editor, debugger, and ISS to the highly optimized Xtensa C/C++ (XCC) compiler that provides excellent code density.
- Both SIMD and 2-way FLIX (parallel VLIW) operations
- Optimized, vectorizing XCC Compiler
- High-performance DSP instruction set
- Dual write ports compute up to three results/cycle
- Supports TI (C6x) and ITU-T C intrinsic code base
- Bit-for-bit compatible with TI C6X code
- C-centric programming model supports standard C 16-bit, 32-bit and 40-bit data types
- Outstanding "out of the box" performance on compiled C source
- Reduces or eliminates the need for assembly code
- Performance acceleration for vectorizable code
- VLIW parallel execution for non-vectorizable code
- Large base of pre-optimized C code
- Quick and easy compiling of C code optimized with TI C6x intrinsics
- Quickly leverage all ITU-T reference code using ITU C intrinsics