Dual-MAC, native 32-bit DSP Architecture

CEVA-TeakLite-III is a third-generation DSP architecture based on the broadly adopted TeakLite family of DSP cores.

For the first time in the TeakLite DSP family, CEVA-TeakLite-III delivers native 32-bit processing and a dual Multiply-Accumulate (MAC) architecture, making the DSP ideal for deployment in High Definition (HD) audio applications requiring advanced audio standards such as Dolby Digital Plus 7.1, Dolby TrueHD and DTS-HD. Additional target applications for CEVA-TeakLite-III include low-cost 2G/2.5G/3G wireless baseband modems, wideband voice and audio processors, portable media players, voice-over-IP residential gateways and dual mode cellular/voice-over-WiFi handsets.

In addition to 32-bit processing power and a dual-MAC architecture, CEVA-TeakLite-III features a 10-stage pipeline, enabling the core to reach operating speeds of up to 550MHz in a 65nm process (worst-case conditions and process). Compared to CEVA-TeakLite, initial performance show it to be up to 4 times faster on basic operations and 2 times better on most popular audio codecs.

For next-generation Hi-Fi audio applications, the CEVA-TeakLite-III inherently supports 32-bit data processing functions with multiple precision points and offers an enlarged 64-bit data memory bandwidth. A FFT accelerator further boosts audio performance and reduces power consumption.

3G multimode and portable audio applications are enhanced through dual 16-bit multipliers, a built-in Viterbi accelerator and a set of SIMD and parallel instructions. By utilizing a 10-stage pipeline, the CEVA-TeakLite-III runs at 380MHz in a 90nm G process, and up to 550MHz in a 65nm G process, using the worst-case corner.

Next-generation wireless and digital media devices require larger program size, increased local frame buffers and efficient multi-tasking. CEVA-TeakLite-III expands its predecessor's addressable memory space by offering a 4 GB linear address space for code and data memory. The core also offers a 32-bit unified general purpose register bank and a 32-bit scalar unit, with arithmetic, logical, bit manipulation and quick look-up-table access capabilities, as well as a branch prediction mechanism, to further enhance its micro-controller feature set.

CEVA-TeakLite-III is a family of DSP cores, configurable to meet specific application requirements. Each of these DSP cores is comprised of the DSP engine data and program memory controllers, cache controllers, system peripherals and system interfaces. CEVA-TL3210 and CEVA-TL3211 are members of the CEVA-TeakLite-III family that are available for licensing today. Each of these DSP cores is to tailored to specific application needs and SoC architectures, and is further configurable to
meet specific requirements. Offering the licensee a complete DSP system allows saving further HW development and integration efforts and ensures
a quick deployment into the target SoC. This also guarantees performance for the complete system, and fast timing closure process at the customer’s end.