IP core architecture supporting both HDMI and MHL connectivity standards in a single-chip solution
Silicon Image is a major supplier of mixed signal transmitter and receiver IP cores that incorporate the latest features of the HDMI® (High-Definition Multimedia Interface) and MHL® (Mobile High Definition Link) connectivity specifications. MHL technology delivers 1080p 60 uncompressed video with up to eight channels of digital audio while charging the mobile device, all through a 5-pin interface. MHL technology allows consumers to connect their mobile devices to a larger screen, such as a DTV or monitor, using existing connections on the mobile and CE products-enabling consumers to enhance their mobile experience by enjoying HD video entertainment, photos, applications, and games on the big screen.
The dual-mode HDMI and MHL transmitter IP core is the industry's first IP core that supports HD video/audio standards - MHL and HDMI. This IP core is intended for integration in SoC (system-on-chip) devices that require the efficient implementation of both HDMI and MHL in a single design that saves on engineering development and SoC photomask and manufacturing costs by sharing SoC die area between HDMI and MHL.
Operating in HDMI mode, Silicon Image's dual-mode transmitter core supports HDMI Version 1.4b including 3D video formats and all 4Kx2K formats. In MHL mode, this IP core supports 1080p 60Hz full HD resolution, native 3D formats and alpha-numeric key codes for advanced remote control capabilities as defined in the MHL 2.0 specification.
The dual-mode IP core supports all relevant audio formats up to 8-channel digital audio, while its color conversion allows convenient interfacing with most video devices. The core is configurable, providing SoC designers access to multiple internal interfaces and hardware blocks, potentially reducing integration time and gate count. The core includes digital logic, analog GDSII, models, software and documentation.
In addition to market-leading HDMI and MHL features, IP cores from Silicon Image offer numerous SoC integrator advantages, including reduced overall bill-of-materials (BOM) costs and lower power use for mobile applications. Silicon Image's industry leadership and unparalleled expertise helps its IP customers accelerate time-to-market through shorter design cycles and faster compliance testing.
Features
- Digital Video Inputs (HDMI & MHL)
- 24/30/36/48-bit RGB/YCbCr 4:4:4
- xvYCC Color
- 16/20/24-bit YCbCr 4:2:2
- 8/10/12-bit YCbCr 4:2:2 (ITU 601 and 656)
- Separate and embedded syncs
- Video Processing
- Resolutions 16-bit 1080p 30 & 12-bit 1080p 60
- Color - space conversion
- 4:2:2-to-4:4:4 and 4:4:4-to-4:2:2 conversion
- Support of all mandatory and many optional
- HDMI 1.4b/MHL 2.0 3D video formats up to
- 1080p 60
- Digital Audio Inputs (HDMI & MHL)
- Industry standard S/PDIF, I2S and parallel input
- Direct Stream Digital (DSD) for Super Audio CD
- Dolby® TrueHD
- DTS-HD Master Audio™ high bit rate (up to 24Mbit/s)
- 2 to 8 Channel Dolby Digital®
- DTS, DVD Audio & PCM support up to 192 kHz
- IEC 60958 and IEC 61937 compatible
- System Operation
- Parallel and Slave I2C I/F, Master I2C (HDCP)
- Interrupt pin and registers
- Monitor detection (hot plug & receiver detect)
- HDCP cipher engine encrypts video/audio
- Programmable Data Enable (DE)
- CEC (Consumer Electronics Control)
- Home Network Support and Audio Uplink (optional)
- HDMI Ethernet Channel
- Audio Return Channel => S/PDIF out
- Compliance - HDMI
- HDMI 1.1, 1.2, 1.3 and 1.4b
- HDCP 1.4
- EIA/CEA-861D
- DVI 1.0
- Compliance - MHL
- MHL 1.2 and 2.0
- HDCP 1.4
- EIA/CEA-861E
- Single Digital IP Core
- Unencrypted, commented RTL
- Interface to analog TMDS Tx PHY
- Development kit and firmware for CEC (option)
Deliverables
- Single Analog IP Core
- TMDS Tx PHY - .lef, .lib, GDSII
- LVS Netlist
- NC-Verilog Test Bench
- Test bench
- I2C and parallel I/F verification modules
- Audio/video stimulus and monitors
- Dual-mode receiver encrypted model
- Regression test suite
- Test-invoking scripts
- Scripts and Documentation
- Synopsys synthesis scripts & constraint files
- Primetime static timing scripts
- ATPG example scripts
- Logic-equivalency scripts - RTL2Gates
- Programming and integration guidelines
- Design overview and I/O description
- Design datasheet
Applications
- Cameras & Camcorders
- Mobile Phones
- Portable Gaming Systems
- Set-Top Boxes
Block Diagram of the Dual-Mode HDMI 1.4b/MHL 2.0 Transmitter IP Core