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Dual-Mode HDMI/MHL Receiver IP Core

IP core architecture supporting both HDMI and MHL connectivity standards in a single-chip solution

The Dual-mode HDMI Receiver and MHL Receiver IP Core supports the latest HDMI 1.4a feature set, including 3D, 4K, HDMI Ethernet Channel and Audio Return Channel, as well as MHL functionality. This dual-mode core includes digital logic, analog GDSII, models, software, and documentation.

The Dual-mode HDMI Receiver and MHL Receiver IP core was developed to support two HD video connectivity standards - MHL and HDMI. In HDMI mode, Silicon Image's Dual-mode Receiver IP core supports HDMI 1.4a features, including all mandatory and optional 3D video formats and all 4Kx2K formats. The dual-mode IP core also supports HDMI Ethernet Channel to send and receive data via 100 Mbps Ethernet over an HDMI cable, while Audio Return Channel allows a TV to send audio streams from the TV to an HDMI attached A/V receiver for improve sound. The built-in Consumer Electronics Control (CEC) connection allows the user to operate multiple devices with one remote control.

In MHL mode, the dual-mode IP core supports video resolutions up to 1080p, allowing mobile devices such as smartphones, HD camcorders and portable media players to display HD content by connecting to HDTVs using existing connections. The built-in Remote Control Protocol (RCP) connection enables the user to operate multiple devices with one remote control.

The dual-mode IP core supports all relevant audio formats up to 8-channel digital audio, while its color space converter allows convenient interfacing with most video interfaces. The core is configurable, providing SoC designers access to multiple internal interfaces and hardware blocks, potentially reducing integration time and gate count. The core includes digital logic, analog GDSII, models, software and documentation. The first implementations of GDSII will be in 55 nm and 65 nm processes. In addition, this IP core supports High-bandwidth Digital Content Protection (HDCP) for both HDMI and MHL modes.

Features

Other Features & Benefits Digital Video Outputs
24/30/36/48-bit Deep Color RGB/YCbCr 4:4:4
x.v.Color
16/20/24-bit YCbCr 4:2:2
8/10/12-bit YCbCr 4:2:2 (ITU-R BT.601/656)
12/15/18/24-bit DMO (Digital Multimedia Output) RGB/YCbCr 4:4:4
Separate and embedded syncs
Video Processing
HDMI mode: up to 1080p60 with 48-bit Deep Color video, 1080p120, 3D formats and 4Kx2Kp30
MHL mode: up to 1080p30
Color space conversion
4:2:2-to-4:4:4 and 4:4:4-to-4:2:2 conversion
Digital Audio Outputs
Industry standard S/PDIF and I2S output
Direct Stream Digital (DSD) for Super Audio CD
Dolby® TrueHD and DTS-HD Master Audio™ high bit rate support up to 24Mbit/s
2/8 Channel Dolby Digital®, DTS, DVD-Audio and PCM support up to 192 kHz
IEC 60958 and IEC 61937 compatible
System Operation
Automatic configuration supported
Parallel and Slave I2C I/F, Slave I2C (HDCP)
Interrupt pin and registers
Monitor detection (hot plug & transmitter detect)
HDCP cipher engine decrypts video/audio
Programmable Data Enable (DE)
CEC (Consumer Electronics Control) for HDMI
Remote Control Protocol (RCP) for MHL
Low microcontroller interaction
Compliance
HDMI 1.4a
HDCP 1.4
MHL
EIA/CEA-861D
Content Protection
HDCP cipher engine decrypts video/audio

Deliverables

Digital IP Core
Unencrypted, commented RTL
Interface to analog HDMI Rx and MHL Rx PHY and HDMI Ethernet & Audio Return Converter IP Core
Example Firmware
Development kit and firmware for CEC (option)
Analog IP Core
HDMI and MHL Rx PHY - .lef, .lib, GDSII
HDMI Ethernet & Audio Return Converter - .lef, .lib, GDSII
LVS Netlist
NC-Verilog Test Bench
Test bench
I2C verification modules
Audio/video stimulus and monitors
HDMI transmitter encrypted model
MHL transmitter encrypted model
Regression test suite
Test-invoking scripts
Scripts and Documentation
Synopsys synthesis scripts & constraint files
Primetime static timing scripts
ATPG example scripts
Logic-equivalency scripts - RTL2Gates
Programming and Integration guidelines
Design overview and I/O description
Design datasheet