The dual mode turbo decoder T-1003 supports 3GPP standard on both LTE and HSPA+ modes. It greatly reduced the memory and logic complexity compared with two separate decoders. It is configurable for mobile devices and base station by a unique architecture designed to reduce the power consumption and gate count while keeping the performance close to an ideal decoder.
- Silicon verified in 32nm process with 500Mhz clock frequency.
- Supports 3GPP WCDMA/HSPA+/TD-SCDMA and LTE modes.
- It provides 220bps throughput in LTE mode with 8 iterations.
- It provides 200bps throughput in HSPA+ mode with 8 iterations.
- The number of MAP engine is up to 8 and is automatically selected for optimal performance.
- Low power consumption by near ideal early termination algorithm applied to both HSPA+ and LTE.
- Near ideal BER/BLER performance.
- Minimum software interaction. Interleaver patterns are generated internally with no external parameter calculations.
- Switching from LTE mode and HSPA+ mode from block to block without cycle loss.
- Licensed to a major chipset maker. It is proven to be able to support UMTS base stations. Silicon validated and running at 500Mhz on 32nm ASIC technology. Logic gate count is about 310K. With 4 iterations, the throughput reaches 500Mbps.
- Synthesizable RTL code/test bench.
- Bit exact C/C++ source code and test bench for simulation integration.
- Design specification.
- BER/BLER Performance report.