BCH codes are mainly used in communication systems requiring Forward Error Correction (FEC) as an error detector and correctors where data transmitted through communication channel is viable to errors and erasures. The BCH encoder receives K symbol code word and appends with 2T symbols and then form N symbol code word. As a result BCH decoder can detect and correct up to T possible symbol errors or up to 2T symbol erasure symbol errors, where T is (N-K)/2.
- 1. High speed BCH encoding algorithm.
- 2. Fully compliant with standard such as DVB-S2 and DVB-S standards.
- 3. Compatible with all code and data lengths.
- 4. Synchronous design.
- 5. Provision to change code rates dynamically.
- 6. Core can be configured for any value of code and data lengths N and K.
- 7. Area and power optimized implementation
- 1. Verilog RTL source code
- 2. The IP core test environment developed in verilog HDL (test benches).
- 3. Synthesis and Simulation scripts.
- 4. Detailed user documentation, including RTL source code documentation.
- 5. • Architecture specification