Embedded Logic Test

Features

• High transition fault coverage, signal integrity screening, and high coverage of unmodeled defects reduces field returns.
• Quick insertion of logic BIST structures, reduced test debug times, and fully reusable embedded test inserted cores shortens time-to-market.
• Minimal tester hardware requirements reduces test costs. A patented test timing architecture for effective at-speed test application and power control.
• Comprehensive RTL or gate-level automation flow for fast test integration. High bandwidth pseudorandom test pattern application for high N-detect (defect coverage).
• IEEE 1500–compliant distributed test access architecture and patented core shared isolation for hierarchical test integration.
• Hierarchical embedded solution means full test portability for cores.
• Provides full test reuse throughout the entire product life cycle.
• No test patterns to manage means a highly predictable hand-off to manufacturing.

Benefits

• Reduce field returns with high at-speed transition fault coverage and high coverage of unmodeled defects.
• Reduce test time with quick insertion of logic BIST structures.
• Shorten time-to-market with fully reusable embedded test inserted cores.
• Reduce test cost with minimal tester hardware requirements.