Implements an Extended Capabilities parallel Port (ECP) that makes a peripheral compliant with the IEEE1284-2000 specification.
The ECP is an asynchronous, byte-wide, bidirectional channel between a peripheral and a host computer. The ECP_Slave core implements the fast ECP mode, and also the forward Compatibility and reverse Nibble modes (useful together for bidirectional support of older devices). It supports Device ID strings in the Nibble and ECP modes, thus permitting the identification of the peripheral on Plug & Play operating systems.
The core also implements run length encoding (RLE) decompression on ECP forward direction transfers, providing real-time data compression ratios up to 64:1 and especially useful for transferring raster images with long strings of identical data.
The ECP_Slave core has been developed for reuse in ASICs and FPGAs and is a fully synchronous design. It has one global clock domain, no latches, and tristate enable signals are provided to combine input and output buses to a single bi-directional bus.
- Compliant with the IEEE 1284-2000 parallel interface protocol standard
- Supports common asynchronous transfer modes:
- ECP Mode — fast, bidirectional, byte-wide transfer
- Compatibility Mode — forward transfer (host-to-peripheral) using the original “Centronics” standard
- Nibble Mode — Reverse (peripheral-to-host) transfer, four bits at a time, with broad compatibility.
- Device ID strings in ECP and Nibble modes support Plug & Play operation
- Performs Run Length Encoding (RLE) decompression in the forward direction for faster transfer of large, regular data (e.g., raster image files)
- Includes Software Development Kit with sample software for Win NT/2000/XP operating systems
- Technology-independent HDL source code
- Sophisticated self-checking Testbench (Verilog versions use Verilog 2001)
- HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
- A Software Development Kit for Win2000/XP operating systems
- Sophisticated self-checking Testbench (Verilog versions use Verilog 2001) including external FIFOs, buffers, models of interfaces, and the core
- Simulation script, vectors, expected results, and comparison utility
- Synthesis script (ASICs) or place and route script (FPGAs)
- Comprehensive user documentation, including detailed specifications and a system integration guide