The Finite Impulse Response (FIR) Filter is the one of the most ubiquitous and fundamental building blocks in DSP systems. Although its algorithm is extremely simple, the variants on the implementation specifics can be immense and a large time sink for hardware engineers today, especially in filter dominated systems like Digital Radios. The FIR Compiler reduces filter implementation time to the push of a button, while also providing users with the ability to make trade-offs between differing hardware architectures of their FIR Filter specification.
Supports Virtex®-7, Kintex®-7, Virtex-6 and Spartan®-6 device familiesSupports AXI4-stream interfaceDelivers VHDL demonstration testbench with CORE GeneratorSupports Pipelined Direct-Form based Multiply Accumulate (MAC) FIR and Transposed Direct-Form based MACFIRHigh-performance finite impulse response (FIR), polyphase decimator, polyphase interpolator, half-band, half-band decimator and half-band interpolator, Hilbert transform, and interpolated filter implementationsAdvanced interleaved channels to enable implementation of configurable bandwidth feature for advanced systemsMulti-column support of DSP48 slices for symmetric filter implementationsA fixed point bit-accurate C-Model to enable system level analysis of Xilinx FIR Compiler coreNew Features in v5.0 :
Features in v6.3
Supports Virtex-7, Kintex-7, Virtex-6, Virtex-5, Virtex-5, Virtex-4, Spartan-6, Spartan-3, and Spartan-3A device familiesSupports Pipelined Direct-Form based Multiply Accumulate (MAC) FIR, Transposed Direct-Form based MACFIR and Distributed Arithmetic (DAFIR) FIRHigh-performance finite impulse response (FIR), polyphase decimator, polyphase interpolator, half-band, half-band decimator and half-band interpolator, Hilbert transform, polyphase filter bank, and interpolated filter implementationsMultiple implementation architectures: DAFIR, Adder Tree based MACFIR (suitable for Mult18x18 enabled devices) and Adder Chain based MACFIR (suitable for XtremeDSP™ slice enabled devices)Key Features in v5.0 and v6.2
Performance reaching up to 470 MHz for Virtex-6, Virtex-7 and Kintex-7 devices (-1 speed grade)Performance reaching up to 470 MHz for Virtex-6 devices (-1 speed grade)Performance reaching up to 250 MHz for Spartan-6 devices (-2 speed grade)Supports 2 -2048 tapsAutomatic control of hardware folding for the most compact implementationSupport for up to 64 channelsInterpolation and decimation factors of up to 64 generally and up to 1024 for single channel filtersSupport for Reloadable Coefficients and up to 16 coefficient setsCapability to share control and coefficient memory resources up to 16 parallel data pathsFloating Point Coefficient entry support and quantization diagnosisAutomatic Coefficient structure optimizations to reduce area consumed: Symmetry and HalfbandSupport for Multiple XtremeDSP slice Column Filter implementationsAutomatic selection of Block vs Distributed Memory for Data and Coefficient storageInstantaneous Resource Estimation of XtremeDSP slice and BRAMBehavioral VHDL model for fast HDL simulationsFor use with Xilinx CORE Generator™ and Xilinx System Generator for DSP