FIR Compiler

The Finite Impulse Response (FIR) Filter is the one of the most ubiquitous and fundamental building blocks in DSP systems. Although its algorithm is extremely simple, the variants on the implementation specifics can be immense and a large time sink for hardware engineers today, especially in filter dominated systems like Digital Radios. The FIR Compiler reduces filter implementation time to the push of a button, while also providing users with the ability to make trade-offs between differing hardware architectures of their FIR Filter specification.

Features in v6.3

Supports Virtex®-7, Kintex®-7, Virtex-6 and Spartan®-6 device families

Supports AXI4-stream interface

Delivers VHDL demonstration testbench with CORE Generator

Supports Pipelined Direct-Form based Multiply Accumulate (MAC) FIR and Transposed Direct-Form based MACFIR

High-performance finite impulse response (FIR), polyphase decimator, polyphase interpolator, half-band, half-band decimator and half-band interpolator, Hilbert transform, and interpolated filter implementations

Advanced interleaved channels to enable implementation of configurable bandwidth feature for advanced systems

Multi-column support of DSP48 slices for symmetric filter implementations

A fixed point bit-accurate C-Model to enable system level analysis of Xilinx FIR Compiler core

New Features in v5.0 :

Supports Virtex-7, Kintex-7, Virtex-6, Virtex-5, Virtex-5, Virtex-4, Spartan-6, Spartan-3, and Spartan-3A device families

Supports Pipelined Direct-Form based Multiply Accumulate (MAC) FIR, Transposed Direct-Form based MACFIR and Distributed Arithmetic (DAFIR) FIR

High-performance finite impulse response (FIR), polyphase decimator, polyphase interpolator, half-band, half-band decimator and half-band interpolator, Hilbert transform, polyphase filter bank, and interpolated filter implementations

Multiple implementation architectures: DAFIR, Adder Tree based MACFIR (suitable for Mult18x18 enabled devices) and Adder Chain based MACFIR (suitable for XtremeDSP™ slice enabled devices)

Key Features in v5.0 and v6.2

Performance reaching up to 470 MHz for Virtex-6, Virtex-7 and Kintex-7 devices (-1 speed grade)

Performance reaching up to 470 MHz for Virtex-6 devices (-1 speed grade)

Performance reaching up to 250 MHz for Spartan-6 devices (-2 speed grade)

Supports 2 -2048 taps

Automatic control of hardware folding for the most compact implementation

Support for up to 64 channels

Interpolation and decimation factors of up to 64 generally and up to 1024 for single channel filters

Support for Reloadable Coefficients and up to 16 coefficient sets

Capability to share control and coefficient memory resources up to 16 parallel data paths

Floating Point Coefficient entry support and quantization diagnosis

Automatic Coefficient structure optimizations to reduce area consumed: Symmetry and Halfband

Support for Multiple XtremeDSP slice Column Filter implementations

Automatic selection of Block vs Distributed Memory for Data and Coefficient storage

Instantaneous Resource Estimation of XtremeDSP slice and BRAM

Behavioral VHDL model for fast HDL simulations

For use with Xilinx CORE Generator™ and Xilinx System Generator for DSP