TrellisWare designed the Flexible Low-Density Parity-Check (F-LDPC) code family to meet the demand for high-performance forward error correction solutions across a wide range of commercial and military applications. The F-LDPC code family offers capacity-approaching performance for all offered code rates and modulations without sacrificing decoder latency or throughput.
The F-LDPC code family is available as encoder and decoder cores for FPGA and ASIC implementations. Standard cores support 8 block sizes, 40 code rates, and 4 modulation types. These cores can be instantaneously reconfigured on the fly: there is zero latency penalty when transitioning from decoding a 128 bit, rate-1/2, BPSK-modulated block to a 16,384 bit, rate-32/33, 16QAM-modulated block.
The F-LDPC is currently deployed in very-small-aperture terminal (VSAT) systems, free space optical (FSO) communication systems, holographic storage systems, a number of military waveforms, and TrellisWare’s own tactical MANET products. Some customers choose the F-LDPC for its throughput (Gpbs+ in FPGAs), while others value the low complexity of implementation. Still others leverage the flexibility of the F-LDPC as a waveform design tool – TrellisWare can add custom block sizes and code rates to the product before or after delivery.
- Unparalleled Flexibility
- Single encoder/decoder core supports any block size, code rate, and modulation combination
- Configurable on-the-fly: Block size, code rate, and modulation can change from block to block with zero latency
- Custom block sizes and code rates can be readily added to standard cores
- Unparalleled Performance
- Capacity-approaching performance across all supported rates
- Low error floors
- High performance for small block sizes
- High-Throughput, Low-Complexity
- Up to 10 Gbps throughput in a single FPGA
- 100Gpbs+ throughputs achievable in ASICs
- Complexity for a given throughput or flexibility significantly lower than competing LDPC and turbo codes