Floating-Point Operator

The extended dynamic range and precision offered by floating-point arithmetic is quickly becoming a requirement in numerous signal processing algorithms that are being used in graphics, advanced wireless communications, instrumentation, industrial control, audio and medical imaging applications. This growing use of floating-point arithmetic places a requirement for area efficient and high performance solutions on hardware engineers of today.

The Xilinx Floating-Point Operator IP provides this solution, giving users the ability to rapidly and easily generate custom operators that can be targeted to any of the latest Xilinx FPGA Platforms. The IP provides all the necessary arithmetic building blocks including: add/sub, multiply, divide, square-root, compare, and data conversion. Furthermore, all operators are IEEE compliant, and highly parameterizable, allowing engineers to control the fraction and exponent word lengths, as well as the latency and implementation specifics.

Features in v6.0:

Supports Virtex®-7, Kintex®™-7, Virtex-6 and Spartan®-6 device families

Supports AXI4-stream interface

Delivers VHDL demonstration testbench with CORE Generator

Support added for reciprocal (1/x) and reciprocal square root (1/sqrt(x)) operations

A bit-accurate C-Model to enable system level simulation of floating point operations

For use with Xilinx CORE Generator™ and Xilinx System Generator for DSP

Features in v5.0:

Supports Virtex-7, Kintex-7, Virtex-6, Virtex-5, Virtex-5, Virtex-4, Spartan-6, Spartan-3, and Spartan-3A device families

Features in v5.0 and v6.0:

Performance reaching up to 470 MHz for Virtex-6, Virtex-7 and Kintex-7 devices (-1 speed grade)

Performance reaching up to 250 MHz for Spartan-6 devices (-2 speed grade)

Supports add/subtract, multiply, divide, compare and square-root operations

IEEE-754 standard compliant floating-point operator (with only minor documented deviations)

Trade-offs between performance and latency with instantaneous feedback on resource and performance estimate

Parameterized fraction and exponent word lengths, including single and double precision

Supports data type converters: Fixed-to-Float, Float-to-Fixed, Float-to-Float

Optimal support of the XtremeDSP™ slice in Floating-Point Multiplier and Adder for Virtex-4, Virtex-5 and Spartan-3A DSP Family

User control of Multiplier implementation: Logic Slice Fabric only, Hybrid Logic Fabric/XtremeDSP, XtremeDSP only

Includes multi-cycle divide and square-root optimizations to trade-off performance for reduced resource utilization

Support for Clock Enable, Synchronous Reset, and Flow Control signals

VHDL behavioral model