FPU is a high-performance arithmetic unit implementing floating-point operations as defined in IEEE Standard for Binary Floating-Point Arithmetic (ANSI/IEEE Std 754-1985).
Supported formats are single precision floating-point numbers (32 bits). Additional supported formats are signed and unsigned integer (for some conversion operations).
It is fully pipelined for execution of the most common FP operations.
All standard floating-point operations are implemented:
• 5 Arithmetic operations: addition, subtraction, multiplying, division and square root.
• 2 conversion operations (conversion between different data precisions – Integer and Floating Point).
• 1 Comparison operation.
• 3 other operations: negate, absolute value and move operations.
- Data precisions: Single precision (32 bits)
- 4 rounding modes: round to zero, round to nearest, round to plus infinity, round to minus infinity.
- Proper processing of Denormalized number.
- Proper processing of Quiet Not a Number, Signaling Not a Number.
- Exceptions generation.
- All standard floating-point operations are implemented.
- All operations (excluding division and square root) are fully pipelined. Each pipelined operation latency is 3 cycles and new operation is received each cycle.
- The latencies of division and square root operations are data depended. Fast operations algorithms that are implemented in the FPU enables very small average latency (average for division – 11 cycles, average for square root – 18 cycles).
- FPU as functional verilog netlist that can be used as separated Floting Point Unit or as part of another module.
- Test System.