The CFV1CORE_ALTERA, available free-of-charge from IPextreme, is the same V1 ColdFire® processor core implemented in Freescale’s MCF51QExx devices, but delivered to you as an SOPC Builder ready design optimized for the Altera Cyclone® III FPGA. The V1 ColdFire system bus has been adapted to the Altera Avalon system interface for the CFV1CORE_ALTERA implementation. However, there are no architectural changes from the standard V1 ColdFire Core, which means the CFV1CORE_ALTERA fully supports the V1 ColdFire Instruction Set Architecture (ISA_C) and is code-compatible with existing V1 ColdFire devices.
The CFV1CORE_ALTERA IP that you receive from IPextreme is fully compatible with Altera’s SOPC Builder and Quartus II tools. That means you can quickly and easily build a system from the CFV1CORE_ALTERA and your selected peripheral IP blocks, then generate a bitfile of the whole system and program it onto your Cyclone III device. You can then download software through the V1 ColdFire single-pin debug interface and start running your application.
A free ColdFire processor on a low-cost, low-power Cyclone III FPGA gives you an ideal solution for both prototyping and production. And, should you want to migrate to an ASIC implementation in the future, you can get the same V1 ColdFire Core from IPextreme as fully-synthesizable RTL source code.
Features
- 32-bit processor core with 24-bit address bus (upper 8 bits of 32-bit Avalon address bus are 0x00)
- Unified instruction/data bus
- Variable-length RISC architecture with 16-bit, 32-bit, and 48-bit instructions
- Independent, decoupled pipelines
- 2-stage Instruction Fetch Pipeline (IFP)
- 2-stage Operand Execution Pipeline (OEP)
- FIFO Instruction Buffer is the decoupling mechanism
- ColdFire Instruction Set Architecture Rev. C (ISA_C)
- Variable-length RISC architecture with 16-bit, 32-bit, and 48-bit instructions
- Standard ColdFire user programming model with 16 general-purpose, 32-bit registers
- Simplified supervisor programming model supporting a supervisor stack pointer, vector base register, and CPU configuration register
- Static branch prediction mechanisms minimize change-of-flow execution time
- Execute engines include ALU and barrel shifter
- Programmable response upon detection of certain illegal opcodes and illegal addresses (processor exception or system reset)
- ColdFire Debug B+ functionality mapped into the single-pin background debug module (BDM) interface
- Real time debug (RTD) support, with 6 hardware breakpoints (four PC, one address, and one data) that can be configured into a 1- or 2-level trigger with a programmable response (processor halt or interrupt)
- In comparison to the configurable V1 ColdFire Core for ASIC implementation, the CFV1CORE_ALTERA is available in a single fixed configuration:
- The hardware divider (DIV) and multiply-accumulate (MAC) unit are not included
- The single-pin debug module is included but the 64-entry trace buffer is not, which means program trace is not supported
Deliverables
- The CFV1CORE_ALTERA is available is available in encrypted RTL for Altera's Quartus II
- The deliverables include:
- Encrypted RTL source code and SOPC component
- Quartus IP license
- Integration Testbench and Test-suite
- Comprehensive Documentation
Video Demo of the Freescale 32-bit V1 ColdFire Processor for Altera Cyclone III
http://youtu.be/Dr_yg8VjL04
Talk to us
Add your Products