Implements a hardware H.264 video encoder that supports the ISO/IEC 14496-10/ITU-T H.264 High Profile specification.
The High Profile H.264 Encoder Core supports real-time encoding of 4:2:0 and 4:2:2 video streams, up to Level 5.2, in 8-, 10-, or 12-bit sample depths. An Intra-only encoder variation features extremely low, sub-frame latency and is suitable for AVC-Intra 50 and AVC-Intra 100 encoder implementations.
The core provides great quality for all types of video and transmission bit rates. Under Constant Bit Rate mode (CBR), it preserves uniform quality while respecting the bit rate—even for the most challenging video content—by making multiple quantization adjustments within a single frame and by selecting the encoding mode based on run-time adaptive models. This allows the core to rapidly adapt to inter- and intra-frame video content variations and the output stream to comply with the hypothetical reference decoder’s coded-picture buffer (HRD-CPB) requirements of the H.264 spec, ensuring uninterrupted video decoding.
The encoder is designed for easy integration. It operates independently of the system processor and features simple interfaces that make system integration straightforward. Furthermore, the core works with any type of external memory and memory controller devices via a flexible external memory interface. Best-practice RTL coding and high-quality deliverables, tested and proven in dozens of designs, ensure that no bad surprises will arise from verification through FPGA or ASIC technology mapping.
Features
- H.264 Video Encoding
- High 10, High 4:2:2, High 4:4:4 (12 bit 4:2:2 or 4:2:0)
- Main and Constrained-Baseline
- Intra versions of all the above
- Supported Video Formats
- 4:2:0 and 4:2:2 YCbCr input with 8, 10 and 12 bits per color sample
- Annex B NAL byte stream output
- Constant Bit Rate (CBR) or variable bit rate Constant Quality (CQP) modes
- High Performance
- Level up to 5.2,
- Up to 240 MBits/s for CAVLC
- Up to 135 MBits/s for CABAC
- High throughput
- 2.5 clocks/pixel for 4:2:0
- 2.75 clocks/pixel for 4:2:2
- Extreme Video Quality
- Advanced rate control operates on sub-frame basis, uses micro-adjustments per MB, and employs run-time adaptive models
- Optimizes rate distortion and perceived video quality
- Respects decoder buffer: HRD CPB compliant CBR output
- Provides uniform quality and rapidly adopts to temporal and spatial video variations
- Wide support of the available coding tools and encoding modes (see Encoding Tools)
- Ease of Integration
- CPU-less, stand-alone operation
- No need for external raster conversion
- Support for planar, interleaved and macroblock input scan
- Flexible external memory interface
- Independent of memory type
- Low bandwidth requirements and tolerant to latencies, for shared memory architectures
- Flexible video input and stream output interfaces
- Flow-controllable, streaming-capable Avalon-ST interfaces
- Optional wrappers for direct connection to an AMBA® AHB or AXI SoC bus
- Run-time tunable operation and on-the-fly target rate changes
- Encoding Tools
- CABAC or CAVLC Encoding
- Motion Estimation
- Optimal, Full-Search
- 32x20 or higher search area; down to ¼ pel accuracy
- Variable block size; up to four motion vectors per MB
- Sophisticated block skipping for fewer motion artifacts in low bit rates
- All Intra prediction modes
- In-Loop deblocking filter
- Multiple slices for error resilience
- Optional thresholding of quantized transform coefficients
Deliverables
- HDL RTL source code (ASICs) or post-synthesis netlist (FPGAs)
- Sophisticated self-checking Testbench (Verilog versions use Verilog 2001)
- Synthesis scripts (ASIC) or place and route script (FPGAs)
- Simulation script, vectors and expected results
- Software (C++) Bit-Accurate Model and test vector generator
- Comprehensive user documentation, including detailed specifications and a system integration guide
Block Diagram of the H.264/AVC High-Profile Video Encoder Core
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