The H.264 Encoder IP core has been developed to be the highest throughput standards compliant hardware H.264 video compressor. Two encoder variants are available to meet the different targets of features, resource usage, and compression:
• H264E-I: H.264 encoder compliant with CAVLC 4:4:4 Intra Profile (all frames are keyframes): the IP core is smaller but yields less compression.
• H264E-P: H.264 encoder compliant with High 4:4:4 Predictive Profile: the IP core is larger but offers a significantly better compression
- Video compression standard ITU.T Rec. H.264 | ISO/IEC 14496-10 AVC.
- EXTREME SPEED, providing a constant throughput of 5.2 pixels encoded per clock cycle.
- Achieves UltraHD on low-end and low-cost Spartan/CycloneI FPGAs
- Realtime configurable VBR/CBR mode (Variable/Constant Bit Rate) automatically controls all H.264 parameters.
- Very low latency (16 lines' time) from first pixel input.
- High 4:4:4 Predictive Profile (H264E-P) and CAVLC 4:4:4 Intra Profile (H264E-I and H264E-P).
- Highest level (5.2) of resolutions and frames per second allowed by H.264 standard attained at just 102 MHz (most mid-range FPGAs).
- Optionally encode beyond the maximum level (5.2) to handle resolutions higher than the H.264 specification (like 8K > Max frame size) and frame rates (for example 4K 16:9 60fps > Max MB/sec), for H.264 decoders which are also capable of above-specification levels.
- Preserves full color fidelity with color subsampling 4:4:4.
- Selectable number of predicted frames (P) per keyframe (I) on H264E-P.
- Selectable number of slices per frame: from one slice per frame to one slice for every 16 lines.
- Output in Byte stream format (raw .264) for easier encapsulation.
- (H264E-P) Full reconstructed video preview output.
- (H264E-I) Optional pseudo-reconstructed video preview output.
- Industry standard interfaces: AXI-Lite slave for configuration/status and AXI3/4 master for pixel-input/encoded-output.
- Embedded DMA engines in AXI3/4 interfaces for direct connection to a memory controller. Support for high latency memories.
- Optional AXI4-Stream Pixel-Input and Encoded-Output interfaces.
- Optional optimized pixel input mode to boost shared memory efficiency.
- Technical support via email
- IP Core Datasheet
- Xilinx EDK drag'n'drop instance
- Altera Qsys drag'n'drop instance
- Linux driver for embedded setups
- Example SW control application
Block Diagram of the H.264 Encoder High Profile (4K on Spartan/Artix/Cyclone)