The Chips&Media’s hardware decoder core BODA950 is a next generation high definition, multi-format video engine that delivers stereoscopic 3D experiences.
The hardware decoder core BODA950 can decode full HD(1080p) video up to 60 frames per second at under 266MHz, supporting multiple video standards, including H.264, MPEG2/4, H.263, VC-1, RealVideo, AVS, as well as advanced video standards such as MVC(Multi-view video codec) and VP8.
By applying a 2-D cache architecture and tiled frame buffer map scheme, the memory access performance and system latency tolerance are improved.
The core is designed to work with 32-bit AMBA APB bus and 64-bit AMBA AXI bus and is targeted at a wide range of 3D capable devices, including 3DTV, 3D camcorder, 3D Blu-ray disc player, 3D-set top box.
Features
- Covers multiple standard in a single core
- ISO/IEC 14496-10 AVC(H.264) BP,MP,HP@L4.2
- ISO/IEC 14496-10/5 MVC Stereo High Profile@L4.1
- ISO/IEC 14496-2 MPEG-4 SP,ASP@L5
- SMPTE 421M-2006 VC-1 SP,MP,AP@L3
- ISO/IEC 13818-2 MPEG-2 MP@HL
- ITU-T H.263(Annex I,J,K,T)
- RealVideo v.8/9/10
- AVS Jizhun @L6.2
- On2 VP8
- Sorenson Spark
- Theora
- Supports up to 2048x2048 resolution
- Simultaneous multi-standard, multiple-stream decoding
- Single H.264 HD(1920x1080p) 30fps decoding at <133MHz core clock
- Dual H.264 HD(1920x1080p) 30fps decoding at <266MHz core clock
- 6SD/D1(NTSC&PAL) 30fps decoding at <133MHz core clock
- Decoding Tools
- H.264 CABAC/CAVLC for lossless compression
- Unrescricted motion vector
- Linear or Tiled memory map
- 2-D smart cache for Motion Compensation(MC)
- Built-in post processing unit
- 90xn degree rotation
- Vertical/horizintal mirroring
- De-ringing
- De-blocking filter for MPEG-2/4
- Interface
- AMBA32-bit APB interface for communication with a host CPU
- AMBA64-bit AXI interface for the external memory
Benefits
- Provides high performance up to 1080p60
- Supports MVC(Multi-view Video Coding) for Blu-ray 3D
- Supports VP8(WebM), Theora as well as H.264 for HTML5
- Full coverage of streams on web browser and internet
- Pre-configurable decoder format enabling SoC designers to optimize for area and power
- Simultaneous decoding of multi-channel, multi-format stream.
- Memory challenge scheme including Tiled buffer map and 2D smart Cache
- Ultra-low power hardware architecture using multi-level clock gating
- Low host CPU resources under 1MIPS
- Proven performance with system level design that minimizes risk and time-to market
Deliverables
- Fully verified synthesizable RTL source code
- RTL test bench
- S/W User Guide
- Datasheet/Integration Guide
- Verification Guide
- Evaluation platform
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see the entire H.264, MVC, VP8, MPEG-1/2/4, VC-1(WMV), RV(RMVB), AVS, H.263, Sorenson Decoding support at 1080p 60fps datasheet
- get in contact with H.264, MVC, VP8, MPEG-1/2/4, VC-1(WMV), RV(RMVB), AVS, H.263, Sorenson Decoding support at 1080p 60fps Supplier
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