The HDMI 1.3 Receiver controller and PHY IP solution provides the necessary logic to implement and verify designs for various consumer electronic applications. The HDMI 1.3 Transceiver IP solution includes a suite of configurable digital controllers and high-speed, mixed-signal PHY IP, thus providing a comprehensive solution from a single IP vendor. The HDMI 1.3 Receiver IP provides designers with a high-performance HDMI sink solution that is extremely low in power and area. With multiple design wins and products shipping in volume, Synopsys' expertise in developing and supporting its DesignWare HDMI 1.3 Receiver IP sink solution enables designers to achieve silicon success for their advanced HDMI solutions. The strict quality measures combined with support from expert technical team enables designers to accelerate time-to-market and reduce integration risk for next-generation consumer electronic applications.
- A superior analog front end that supports up to 20 feet category 2-certified HDMI cables, while maintaining high performance
- Digital controllers delivered in configurable RTL allows designers to optimize gate count and power consumption by choosing only the features required in their application
- PHY offers low power consumption and small die area/Numerous optional features such as High-bandwidth Digital Content Protection (HDCP) encryption engine, various audio formats, audio DMA engine and multiple system-bus interfaces help to ease the integration effort
- System validation based on the Synopsys Confirma HAPS-51 rapid prototyping platform
- Application notes
- Assembly guidelines
- Design files kit: Behavioral model; LEF file; LIB file; GDSII layout database