The HDMI 1.3 Receiver IP Core is compliant with the HDMI 1.3 Specification and is designed for consumer electronics products receiving premium digital content. This core is ideal for next-generation digital TVs, projectors and A/V receivers, and incorporates an extremely flexible audio and video interface. Industry standard S/PDIF is included for PCM encoded data as well as Dolby Digital, DTS and other formats capable of being sent over S/PDIF. I2S and Direct Stream Digital (DSD) interfaces are included to support Dolby® TrueHD and DTS-HD Master Audio high bit rate and Super Audio CD formats. The HDMI core provides full support for HDCP decryption and authentication.
Two options exist for the HDMI Receiver PHY. For the highest level of integration, Silicon Image offers the PHY as an IP core which is tightly coupled with the digital logic. For designers looking for faster integration and process independence, there is the HDMI digital transmitter core plus discrete companion PHY (SiI 9003).
All cores are semiconductor-proven at leading foundries and through Silicon Image HDMI semiconductor products.
Available in .18u, .13u, 90nm, 45nm and 40nm.
Features
- Compliance
- HDMI 1.3
- EIA/CEA-861D
- DVI 1.0
- HDCP 1.2
- Video Outputs
- 24/30/36-bit RGB/YCbCr 4:4:4 (Deep Color)
- 16/20/24-bit YCbCr 4:2:2
- 8/10/12-bit YCbCr 4:2:2 (ITU601 and 656)
- 12/15/18-bit DMO (Digital Multimedia Output) RGB/YCbCr 4:4:4
- Separate and embedded syncs
- xvYCC extended color space
- Video Processing
- 480i/p, 576i/p, 720p, 1080i/p
- PC resolutions (VGA/XGA/SXGA/UXGA)
- Color space conversion
- 4:4:4-to-4:2:2 and 4:2:2-to-4:4:4 conversion
- Digital Audio Outputs
- Industry standard S/PDIF and I2S output
- Direct Stream Digital (DSD) for Super Audio CD
- Dolby TrueHD and DTS-HD Master Audio high bit rate support up to 24Mbit/s
- 2/8 Channel Dolby Digital, DTS, DVD-Audio and PCM support up to 192 kHz
- IEC60958 or IEC61937 compatible
- PHY Options
- HDMI Rx PHY IP Core
- SiI 9003 discrete PHY
- System Operation
- Register-programmable via slave I2C
- Slave I2C (HDCP)
- Interrupt pin and registers
- Monitor detection (hot plug & transmitter detect)
- Programmable Data Enable (DE)
- HDMI CEC
- Content Protection
- HDCP cipher engine
- Decrypts video/audio
Deliverables
- Digital IP Core
- Unencrypted, commented RTL
- Interface to TMDS receiver PHY IP or SiI 9003 external PHY
- Analog IP Core
- TMDS receiver - .lef, .lib, GDSII
- LVS Netlist
- NC-Verilog Test Bench
- Test bench
- I2C verification modules
- Audio/video input stimulus
- Audio/video output monitors
- HDMI transmitter encrypted model
- Regression test suite
- Test-invoking scripts
- Scripts
- Synopsys synthesis scripts & constraint files
- Primetime static timing scripts
- ATPG example scripts
- Logic-equivalency scripts – RTL2Gates
- Documentation
- Programming and Integration guidelines
- Design overview and I/O description
- Design datasheet
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