Synopsys' DesignWare® Logic Libraries provide a broad portfolio of high-speed, high-density and low-power standard cell libraries, providing a complete standard cell platform solution for a wide variety of system-on-chip (SoC) designs. In addition to Synopsys' silicon-proven standard cell libraries, available Power Optimization Kits (POKs) and Engineering Change Order (ECO) Kits deliver outstanding performance, with low power and small area in the advanced nodes of leading foundries.
Ideal for tablet, smartphone, cell phone, graphics, networking, storage and other high-performance applications requiring low power and high density, Synopsys' DesignWare Logic Libraries and Memory Compilers provide a unique set of options that enable SoC designers to optimize their products for speed, area, dynamic power, standby power and cost.
- Maximum Performance - High-performance libraries for critical paths of GHz processors; Close timing in fewer iterations without sacrificing area or power
- Minimum Power - Multi-channel libraries for 4X-5X static power reduction; Power Optimization Kits with over 200 cells; Support for low-power UPF and CPF EDA flows
- Maximum Density - Patented NXT standard cell architectures for highest routing utilization; Multiple cell heights per process (~7, ~9 and ~12 track) for optimal tradeoffs; Hand-crafted layout for maximum density
- High Yield - Design-for-manufacturing (DFM)-aware design and validation; Redundant contacts; Electro-migration (EM)-compliant at highest speeds
- Comprehensive Solution - Electrically, physically and EDA-view aligned with DesignWare Embedded Memory products; Multi-VDD characterization with low voltage and overdrive PVTs
- Multiple Libraries per Process Node
- Multiple Cell Architectures for Optimal Power, Performance and Area
- Optimized Cell Sets; Accurate Characterization
- Availability of Process, Voltage and Temperature (PVT) Characterization Corners - Standard, overdrive and low voltage PVT clusters for timing and leakage; PVTs aligned with DesignWare Memory Compiler PVTs; Custom PVT development available
- Silicon proven using Split Lots at Advanced Nodes - Correlated to EDA models; Low voltage testing to VDDMin
- CDL and other industry standard design views